Hi,
What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for Verilog)? I've tried using " synthesis attribute register_duplication xx "yes" " (closest thing I found so far that may be what I'm looking for) with xx equal to the module name, the module instance, the signal...nothing seems to work. I have register dulpication selected in the properties for "implement design"...
Any help appreciated.
Austin