Hi,
What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for Verilog)? I've tried using " synthesis attribute register_duplication xx "yes" " (closest thing I found so far that may be what I'm looking for) with xx equal to the module name, the module instance, the signal...nothing seems to work. I have register dulpication selected in the properties for "implement design"...
Any help appreciated.
Austin
I found "equivalent_register_removal", but so far, that hasn't worked either...but that seems to be the right attribute, now I just have to get it to work...as register_duplication is apparently not the right attribute.
Hi Austin,
Please, have a look at an example, where I had used the attribute in XCF: Here "zbtcntr_double_width" is the entity name and RD_WRl_TRId2(0) is the register which I wanted to preserve.
1)MODEL "zbtcntr_double_width" equivalent_register_removal= false; #Use the above attr. , if you want it to be applicable to the whole module or entity.2)BEGIN MODEL "zbtcntr_double_width" NET "RD_WRl_TRId2(0)" equivalent_register_removal= false; #Use the above attr. if you want to preserve a particular Reg.
HTH Ajay Panicker CG-CoreEL
Aust> I found "equivalent_register_removal", but so far, that hasn't worked
Hi,
I figured out how to get it to work. There is a flag in the synthesis options to enable/disable this...that seemes to work, but obviously globally.
To get it to work on individual registers, instead of globally, the directive seems like it has to be after the reg statement. I'm not sure why as the documentation shows that you have to name the register specifically in the directive...except that perhaps it's a single pass compiler. I had the directive just above the reg statement...and it complained it couldn't find the reg. Putting it on the same line worked.
Austin
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