Output register instantiation in Quartus

Instead of making assignments using the Assignment Editor it is possible to make these assignments inside your HDL. For examples please see Pgs 8-41 to

The Section heading is "Setting Other Quartus II Options in your HDL source code". The specific subsections that will be of interest to you are "Use I/O Flip Flop" and "Altera Attribute".

Hope this helps, Subroto Datta Altera Corp.

I have been using the following component for Lattice devices when I want a signal to be routet into a fast output register:

ODDRXB_RASN : ODDRXB PORT MAP ( Da => ls_ddr_rasn_h1, Db => ls_ddr_rasn_h1, Clk => Clk90, Lsr => Reset, Q => DdrRasn );

As you can see the module ODDRXB can be instantiated within the VHDL module.

Now I want to do something similar in QuartusII version 5.0 software. The only way I know is to tell the fitter in the Assignment Editor that you want signals to be routet into output registers. Is there a possibility to instantiate an output register module within my VHDL module whithout using the Assignment Editor ?

Any hints are appreciated.

Rgds André

Hi Subroto,

thank you for the link.

One more question:

I have put the attributes into my VHDL code. (in the ENTITY declaration).

After compilation and synthesis I can see in the "Fitter Netlist Optimizations" that the signals have been routed into Fast Output Registers. But where do I see that in the Assignment Editor ? Is it visible there at all ?

Are the attributes also valid if I use them in a submodule of my design ?

Rgds Andr=E9

Assignments made in the HDL files cannot be seen in the Assignment Editor.

However you can make the following assignments in a submodule: The useioff or altera_attribute="fast_output_register=on", can be made on the submodule of a design because it is really an assignment to a register to tell it to be packed into the I/O. Most other assignments (e.g. chip_pin to give a pin location) cannot be made on a submodule. Hope this helps, Subroto Datta Altera Corp.

thank you for the link.

One more question:

I have put the attributes into my VHDL code. (in the ENTITY declaration).

After compilation and synthesis I can see in the "Fitter Netlist Optimizations" that the signals have been routed into Fast Output Registers. But where do I see that in the Assignment Editor ? Is it visible there at all ?

Are the attributes also valid if I use them in a submodule of my design ?

Rgds André

Thanks Subroto,

you are always a great help.

Rgds Andr=E9

Hi Subroto,

I think the use of attributes in VHDL modules can be helpful for the purpose of clearness and readability.

Regarding tristate buffers I have the following additional question:

Let's assume the following description of a bidirectional bus with tristate buffer:

ENTITY xy IS PORT ( ... DataInOut : INOUT std_logic_vector(15 downto 0); ... END xy;

ARCHITECTURE gt OF xy IS BEGIN DataInOut 'Z'); -- with ls_datareg and ls_drive being registers.

END gt;

What does the Altera fitter do if I use the useioff attribute for the bidirectional DataInOut ? Does the fitter implement fast input registers as well as fast output registers ?

Best regards Andr=E9

Hi Andre,

There are two separate attributes; one for input registers and one for output registers.

Use "fast_input_register = on" to put a register that is capturing an input to the FPGA from an I/O cell into the I/O cell. Use "fast_output_register = on" to put a register that is storing a value that drives an I/O cell (either the data port or the OE port) into the I/O cell.

You can set these attributes either on registers or on I/O cells. So if you have a bidirectional I/O, and want both the input path and output path registers for the signals into and out of the I/O cell to be implemented in the I/O cell, set the altera_attribute on the I/O to be: "-name fast_input_register = on; -name fast_output_register = on"

Alternatively, you can just set timing constraints on your I/O paths in Quartus, and it will move registers into the I/O cells if that will improve your timing. In that case, you don't need to make any fast register assignments. You should really make I/O timing assignments no matter what, since (1) you want to know if you violate a constraint on your design, and (2) there are other I/O timing optimization decisions Quartus makes besides just where to put the registers connected to an I/O, and those optimizations need timing constraints to guide them.

Regards,

Vaughn Altera [v b e t z (at) altera.com]

I think the use of attributes in VHDL modules can be helpful for the purpose of clearness and readability.

Regarding tristate buffers I have the following additional question:

Let's assume the following description of a bidirectional bus with tristate buffer:

ENTITY xy IS PORT ( ... DataInOut : INOUT std_logic_vector(15 downto 0); ... END xy;

ARCHITECTURE gt OF xy IS BEGIN DataInOut 'Z'); -- with ls_datareg and ls_drive being registers.

END gt;

What does the Altera fitter do if I use the useioff attribute for the bidirectional DataInOut ? Does the fitter implement fast input registers as well as fast output registers ?

Best regards André

Hi Subroto,

on

But the handbook says the following: The useioff synthesis attribute takes a Boolean value and can only be applied to the port declarations of a top-level Verilog HDL module or VHDL entity (it is ignored if applied elsewhere).

So is it not possible to use "useioff" in submodules ?

Rgds Andr=E9

Andre, I had this investigated some more. There is a difference between the software functionality and the Handbook, but the Handbook is the official line here. So the correct way to pack a register into an I/O from anywhere in a design that is guaranteed to work in any future Quartus release is to make a fast_output_register assignment on the register. Today it will work if you make a fast_output_register assignment on a lower-level I/O, but this is not officially supported and not guaranteed to work in a future release. example syntax:

signal my_reg : std_logic;

attribute altera_attribute : string ; attribute altera_attribute of my_reg : signal is "-name fast_output_register on";

Hope this helps, Subroto Datta Altera Corp.

But the handbook says the following: The useioff synthesis attribute takes a Boolean value and can only be applied to the port declarations of a top-level Verilog HDL module or VHDL entity (it is ignored if applied elsewhere).

So is it not possible to use "useioff" in submodules ?

Rgds André