Latest threads in Field-Programmable Gate Arrays

fixed point dot product with log2(n) pipe stages in vhdl

I would like to write a parameterizeable component in vhdl that would do an N element fixed point dot product. I was wo...

1 21yrs

wallge

1 21yrs wallge

Xilinx ISE 7.1i Portability Error

Has anyone else received this error with ISE 7.1i? I added a peripheral to my embedded system, and when I re-synthesize...

2 21yrs

maplante

2 21yrs maplante

Xilinx dev board with high quality video?

I'm doing a proof of concept that requires high quality video out. Either RGB or composite is fine (both would be great...

21 21yrs

pfraser

21 21yrs pfraser

PCB Software....

Hi All, I am developing a board using Virtex FPGA. Right now i am using Protel, but i am not being able to use the "Equ...

7 21yrs

henrique.portela

7 21yrs henrique.portela

I, Wish: I had an Spartan-3e NOW!

as topic says. any device in any package as chip only (can be bga as long as its not bare die) or soldered on board (th...

3 21yrs

antti

3 21yrs antti

Lattice XP availability

Hello all, Anybody knows when we can expect LFXP3 & LFXP6 in regular distributor channels? Thanks, M.

3 21yrs

veselic

3 21yrs veselic

Prevue - FPGA Dev Board Sale

For all the hardened FPGA addicts and please excuse the sales push. If anyone is interested in our lower spec Broaddown...

3 21yrs

removethisthenleavejea

3 21yrs removethisthenleavejea

Testbench using Modelsim/VHDL - simple signal generation problem

I'm not sure if this is VHDL or Modelsim issue (other than operator issue), so I'm posting in both groups. It looks lik...

11 21yrs

fastgreen2000

11 21yrs fastgreen2000

Power on reset generation in FPGA

Hi all, I have a question on POR(Power on reset generation ) using FPGA. My FPGA does not have a external Power ON rese...

6 21yrs

praveen.kantharajapura

6 21yrs praveen.kantharajapura

Spartan II, Platfrom Flash, ISE 7.1 - SERIOUS PROBLEM

Hi we have one desing (several PCBs tested) where we witness sever problem configuring the XC2S200 and/or XCF02s, on on...

0 21yrs

antti

0 21yrs antti

looking for 1 beta-tester for PLD2HDL (XPLA3 edition) tool

Hi we are looking for one serious beta tester for our PLD2HDL conversion tool (Xilinx Coolrunner XPLA3 support). Please...

0 21yrs

antti

0 21yrs antti

Prob in Synthesizing and Simulating large Mux

Hi all, I am developing a hardware in which I need large size MUX. I need a 240 to 1 byte multiplexer. I tried to code...

16 21yrs

vssumesh_asic

16 21yrs vssumesh_asic

Help! I lost my life (Again)!

Hi I am a need of help to get back something that could be considered 'my life' - its actually a content of an 60GB IBM...

0 21yrs

antti

0 21yrs antti

Altera why so QUIET !?

Hi Altera used to make so much noise here, that I could not belive my eyes seing Stratix-II GX devices at Altera websit...

16 21yrs

antti

16 21yrs antti

best SPI flash configuration solution for Xilinx FPGA's

Hi the standard SPI flash devices are cheap so all FPGA vendors are adding support for them, either directly in the FPG...

1 21yrs

antti

1 21yrs antti

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