I would like to write a parameterizeable component in vhdl that would do an N element fixed point dot product. I was wondering if there was a (synthesizable) way to generate a first stage of multiplies (ceil(N/2) multiply blocks), and then ceil(log2(N)) - 1 add stages. I would like to be able to use generics to specify the length of the vector and the bit width (this in turn specifies the length of the MAC pipeline).
Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
wallge@eng.fsu.edu
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ECE Machine Intelligence Lab
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