Testbench using Modelsim/VHDL - simple signal generation problem

Not seeing more of your testbench, it is difficult to diagnose, but maybe, your "free-running clock" is something like this:

process begin loop clock

Try it again with the signal assignments before the waits.

-- Mike Treseler

Yes, I'm doing just that for creating clock, and your post shed some light on what I wasn't paying attention to, but...

I'm still confused. In the following testbench code, shouldn't it wait for a certain rising edge (whatever time it might correspond to), and assert 'sig1', at the time reported by 'now'? What I see is 'sig1' get asserted one clock after that.

line 1 : wait until rising_edge(clk); line 2 : write (L, string'("1st rising edge : " & image(now))); line 3 : writeline (output, L); line 4 : sig1

Sure thing. But when I do that, I expect the signal assertion duration has shifted as well. I can fiddle the code to do whatever I want it to do, but I'm trying to figure out why it mismatches with my expected behavior... maybe I wasn't clear in my original posting...

So you tell me that now is printed as 314 ns, but sig1 rises at 318 ns? If that is so, it is unexpected for me too!

If you can boil down what you are seeing to under 20 lines of code, and post the 20 lines, I think people will be in a better position to identify the issue.

-Newman

I simulated your code with modelsim, and aside from different times:

I'm glad you don't see the same problem, because that would've puzzled others as well.

Would you mind posting what your testbench looks like? I initially suspected my clock generation as Zara suggested, but that doesn't quite make sense to me. I'll use process of elimination on differences and see what's causing this. I'll post the result as well.

TIA.

Watch out for line wrap...

library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_textio.all ; use std.textio.all ;

entity test is end entity test;

architecture tester of test is constant CLK_PRD : Time := 10 nS; signal Clk : std_logic; signal sig1 : std_logic; begin

tester_p: process is file output : text open write_mode is "test.out"; variable L : line; begin sig1

It would be a case if delta cycle in simulator is set to the sam value as clk period

If you see it go high late.. then it would tend to disagree with the results you printed on the first page.

In saying that.. if you are looking in the wrong place this is quite possible if you are peeking in a process.. then check the sensitivity list.. that's the usual culprit when things don't happen when you expect.

Simon