I'm not exactly sure what the original poster was asking, but I use an SRL16(xilinx) initialised to X"FFFF", configured as 16 bit shift reg, and a '0' at the D input. Once Done goes high, GWE, GSR, etc are released(order of these dependent on bitgen options), the shift reg shifts in the '0' and after 16 clock cycles it appears at the SRL16 Q output. The Q output drives the reset I code into my design(active high). This insures my design reset is removed synchronous to my clock and the path is covered by my clock period timing constraint.
(beware that the GSR net is high fanout and can have significant delay/skew depending on your clock frequency. I never found any timing specs for the GSR net in the Sparatan 3 FPGA datahseet...but there are plenty of posts about it. There is also a good tech exclusive(ken chapman) on the xilinx site talking about the use of resets in your FPGA design.)