Field-Programmable Gate Arrays

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.lib file for Xilinx FPGAs?

Hi everybody, With ASICs, there are standard cell libraries in .lib file format for the target process -- is there a com...
5 comments posted 20yrs
posted by sheinzle
5 comments posted 20yrs posted by sheinzle

evaluation edk in Spartan-3 starter kit

The Xilinx website isn't too clear with respect to the evaluation EDK included with the Spartan-3 starter kit. Does any...
12 comments posted 20yrs
posted by aholtzma
12 comments posted 20yrs posted by aholtzma

Xilinx ISE 7.1i file management

Anyone, I am looking for information concerning the neccissary files required from a completed project to reuse in a ne...
1 comments posted 20yrs
posted by cyd
1 comments posted 20yrs posted by cyd

XMD and xilmfs help

Hello, I have a board with 256M of RAM and a V2P30. Designed a simple system in EDK with the RAM partitioned into 2 equ...
1 comments posted 20yrs
posted by joeylrios
1 comments posted 20yrs posted by joeylrios

I'm desperate... EDK project simulation

Hello I have a system implemented in hardware and I prototyped it i VIrtex-II Pro platform with a testbench. I analyzed...
7 comments posted 20yrs
posted by mvetromille
7 comments posted 20yrs posted by mvetromille

Systolic array architectures

Systolic array architectures are commonly used for image/video compression hardware blocks (e.g. convolution filters, m...
3 comments posted 20yrs
posted by timotoole
3 comments posted 20yrs posted by timotoole

ise (lin64) and debian

Hi, i spend one week to figure out how this combination could work - with no success. currently we install the rh ws 3....
2 comments posted 20yrs
posted by tirmen
2 comments posted 20yrs posted by tirmen

Radiation + CoolRunner2 CPLD?

Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not designed to be radiation tollerent, but... I would be...
4 comments posted 20yrs
posted by bob
4 comments posted 20yrs posted by bob

Xilinx IMPACT Problem... detects 101 unknown devices

Hi all, I have a custom designed hardware.... when i ran the xilinx iMPACT to configure the device, it ended up detecti...
12 comments posted 20yrs
posted by subhasri.krishnan
12 comments posted 20yrs posted by subhasri.krishnan

Altera NIOS PIO interrupt problem

Hello all, I am monica from germany.I am using NIOS in cyclone FPGA.I have problem with PIO interrupts. Environment det...
1 comments posted 20yrs
posted by monica_dsz
1 comments posted 20yrs posted by monica_dsz

High Load

Hallo, I have made a clock divider using a counter connected to master clock and a comparator. The comparator has a clo...
8 comments posted 20yrs
posted by marcotoschi
8 comments posted 20yrs posted by marcotoschi

Floating point multiplication on Spartan3 device

Hi, All. Nowdays I'm focusing on building some design for multiplication of matrices that each element is floating poin...
7 comments posted 20yrs
posted by codejk
7 comments posted 20yrs posted by codejk

Avoiding meta stability?

Is the following a good way to avoid meta stability problems? The signal 'd' is synchronous to a1.8 MHz clock? At least...
51 comments posted 20yrs
posted by billbill
51 comments posted 20yrs posted by billbill