Latest threads in Field-Programmable Gate Arrays

Actel Libero upgrade - problem with clk pin - Synplify

Good morning, I had a design wich was working fine in Libero 6.0 SP3 (Synplify 7.51A). I made an upgrade to Libero 6.2...

4 21yrs

mvq

4 21yrs mvq

.lib file for Xilinx FPGAs?

Hi everybody, With ASICs, there are standard cell libraries in .lib file format for the target process -- is there a com...

5 21yrs

sheinzle

5 21yrs sheinzle

evaluation edk in Spartan-3 starter kit

The Xilinx website isn't too clear with respect to the evaluation EDK included with the Spartan-3 starter kit. Does any...

12 21yrs

aholtzma

12 21yrs aholtzma

Xilinx ISE 7.1i file management

Anyone, I am looking for information concerning the neccissary files required from a completed project to reuse in a ne...

1 21yrs

cyd

1 21yrs cyd

Where to get informations about Virtex 4 FX Engineering Samples

Hi! I just asked my distributor for availiable Xilinx XC4VFX devices and found an XC4VFX20-10FF672CES2. Since I guess t...

5 21yrs

usenet

5 21yrs usenet

XMD and xilmfs help

Hello, I have a board with 256M of RAM and a V2P30. Designed a simple system in EDK with the RAM partitioned into 2 equ...

1 21yrs

joeylrios

1 21yrs joeylrios

I'm desperate... EDK project simulation

Hello I have a system implemented in hardware and I prototyped it i VIrtex-II Pro platform with a testbench. I analyzed...

7 21yrs

mvetromille

7 21yrs mvetromille

Systolic array architectures

Systolic array architectures are commonly used for image/video compression hardware blocks (e.g. convolution filters, m...

3 21yrs

timotoole

3 21yrs timotoole

How to make XST understand to pack mux(A,B,A+B) in a single level ?

Hello, Here is my problem : I want to have a combinatorial block with 4 inputs : - 2 vectors A and B - 2 control signal...

8 21yrs

com.246tNt

8 21yrs com.246tNt

ise (lin64) and debian

Hi, i spend one week to figure out how this combination could work - with no success. currently we install the rh ws 3....

2 21yrs

tirmen

2 21yrs tirmen

Radiation + CoolRunner2 CPLD?

Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not designed to be radiation tollerent, but... I would be...

4 21yrs

bob

4 21yrs bob

Xilinx IMPACT Problem... detects 101 unknown devices

Hi all, I have a custom designed hardware.... when i ran the xilinx iMPACT to configure the device, it ended up detecti...

12 21yrs

subhasri.krishnan

12 21yrs subhasri.krishnan

Altera NIOS PIO interrupt problem

Hello all, I am monica from germany.I am using NIOS in cyclone FPGA.I have problem with PIO interrupts. Environment det...

1 21yrs

monica_dsz

1 21yrs monica_dsz

High Load

Hallo, I have made a clock divider using a counter connected to master clock and a comparator. The comparator has a clo...

8 21yrs

marcotoschi

8 21yrs marcotoschi

Floating point multiplication on Spartan3 device

Hi, All. Nowdays I'm focusing on building some design for multiplication of matrices that each element is floating poin...

7 21yrs

codejk

7 21yrs codejk

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