How to make XST understand to pack mux(A,B,A+B) in a single level ?

In verilog I'd try to use: q

Actually, I don't see how to fit your representation (useA useB) into a single level ...

What I wanted the tool to do is : (pt_n is not passthru)

. cout . _|_ . ,--/___\ CYMUX . | | | . ______ | | | . a(b) ---------| | | | | ____ XORCY . b(n) ------x--| LUT4 |-x----------\\ \_____ . pt_n ---x--|--| | | x----//___/ . sel ---|--|--|______| | | . | | / | . | | __ / | . | '------| \ _/ cin . '---------|__/ . MULT_AND

Sylvain

I wanted something similar but could not get the synthesis tool to generate the circuit, so I instantiated my own.. here it is, you can change the INIT values of the LUT to get what you want.

-----------------------------------------------------------

-- MUX_ADD_VECTOR - when ADD = '1' add O = A + B else O = C

----------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.vcomponents.all;

entity MUX_ADD_VECTOR is

generic (WIDTH : integer := 32; SLICE : integer := 1);

port (A : in std_logic_vector (WIDTH-1 downto 0); B : in std_logic_vector (WIDTH-1 downto 0); C : in std_logic_vector (WIDTH-1 downto 0); ADD : in std_logic; O : out std_logic_vector (WIDTH-1 downto 0));

end MUX_ADD_VECTOR;

architecture XILINX_virtex of MUX_ADD_VECTOR is component LUT4_L generic(INIT : bit_vector); port (LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component;

component MUXCY_L port(LO : out STD_ULOGIC; CI : in STD_ULOGIC; DI : in STD_ULOGIC; S : in STD_ULOGIC); end component;

component XORCY port(O : out STD_ULOGIC; CI : in STD_ULOGIC; LI : in STD_ULOGIC); end component;

component MULT_AND port(LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC); end component;

-------------------------------------------------------

-- Input mapping for LUTs

-------------------------------------------------------

-- I0 -> A (i)

-- I1 -> ADD

-- I2 -> B(i)

-- I3 -> C(i)

-- LO -> otemp(i)

-------------------------------------------------------

-- C(i) B(i) ADD A(i) LO -> Output

-------------------------------------------------------

-- X 0 1 0 INIT[2,A] -> 0

-- X 0 1 1 INIT[3,B] -> 1

-- X 1 1 0 INIT[6,E] -> 1

-- X 1 1 1 INIT[7,F] -> 0

-- 0 X 0 X INIT[0,1,4,5] -> 0

-- 1 X 0 X INIT[8,9,C,D] -> 1

--------------------------------------------------------------

-- INIT F E D C - B A 9 8 - 7 6 5 4 - 3 2 1 0

-- 0 1 1 1 1 0 1 1 0 1 0 0 1 0 0 0 -->

X"7B48"

--------------------------------------------------------------

signal otemp : std_logic_vector (WIDTH-1 downto 0); signal mando : std_logic_vector (WIDTH-1 downto 0); signal carry : std_logic_vector (WIDTH downto 0);

attribute BEL : string;

begin -- XILINX_virtex

carry(0) X"7B48") port map (I0 => A(i), I1 => ADD, I2 => B(i), I3 => C(i), LO => otemp(i));

mux_add_mand_inst : MULT_AND port map (I0 => A(i), I1 => ADD, LO => mando(i));

mux_add_mxcy_inst : MUXCY_L port map (DI => mando(i), CI => carry(i), S => otemp(i), LO => carry(i+1));

mux_add_xorc_inst : XORCY port map (CI => carry(i), LI => otemp(i), O => O(i)); end generate mux_add;

end XILINX_virtex;

Quark....

Following diagram modified for useA and useB above:

Yeah, I confused the two choices of CYMUX ... My bad. The two representation works just fine.

But XST doesn't understand yours either ... it also uses two level with useA and useB ...

Sylvain

that

for

the

yup, I created a "test" entity just for that (to avoid long synthesis of the whole stuff each time I test a thing).

John_H wrote:

Jan Gray wrote about this a couple of times on

Apparently the mapper tries many (or even all) factorizations of your logic but it does not reorder the circuit. Therefore, if you have an adder followed by a mux you get two levels of logic. You need to write down a formulation were the adder follows the remining logic:

result