.lib file for Xilinx FPGAs?

Hi everybody,

With ASICs, there are standard cell libraries in .lib file format for the target process -- is there a comparable .lib file for the Xilinx FPGAs?

Best regards, Simon

Reply to
Simon Heinzle
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yes and no.

Xilinx and Altera both have 'standard' libraries. They are VHDL, Verilog, schematic ..... you can guarantee them to be different as the underlying structure is different.

Mostly they have their built-in's (pin definitions, LUTs block rams etc) but you can often find 74 series gates too. Xilinx has a rather nice core gen to build more complex functions.. some are free some cost. Mostly it depends on what you want from your library

Simon

Reply to
Simon Peacock

First of all, thanks for the reply!

Could these 'standard' libraries be used for timing analysis, e.g. for a core gen normally used for ASICs (to get a rough but more meaningful timing analysis than without any information)?

Best regards, Simon

Reply to
Simon Heinzle

There are macro libraries but no standard cell libraries. Subject tree based mappers do not work well for FPGAs and the timing models used in ASIC flows don't either. Also, you do not need the geometrical information contained in the library because you do not move cells around or connect wires to them at specified locations. So there is no use for a standard cell library with FPGAs.

FPGAs either use muxes as their basic elements (rare nowadays) in which case BDD-based synthesis is the natural approach. Or they use lookup tables that can implement any function with up to N inputs (predominant architecture). In that case listing all possible functions in a library isn't really helpful.

Kolja Sulimma

Reply to
Kolja Sulimma

No.

But: Your asic synthesis tool probably supplies a minimal example library. (Our design compiler here for example has an AND-OR-NOT library with only three cells) You can generate the core from that and then export the resulting netlist as VHDL. Then you can add entities for the three cells and run the result through WebPack. (Free download) The result will be exact in the sense that the circuit really operates in an FPGA at the resulting frequency. But of course your core generator likely has made some design decisions that are really suboptimal for FPGAs.

Kolja Sulimma

Reply to
Kolja Sulimma

Once Again: Thanks a lot guys!

Best regards, Simon

Reply to
Simon Heinzle

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