Latest threads in Field-Programmable Gate Arrays

Problems in simulating EDK system

Hello! I want to debug my system generated in EDK, so I'm using ModelSim. I generated the simulation files and created...

0 20yrs

mvetromille

0 20yrs mvetromille

vhdl question

please someone let me know the effects of having "ibuf_lvcmos33" for each input , "obuf_lvcmos33" for each output and "...

12 20yrs

manusha

12 20yrs manusha

going backwards, Xilinx ISE 7.1 to ISE 6.3

I own and use Xilinx ISE 7.1 BaseX and to develop Spartan-3 code. I have a client who owns and uses ISE 6.3 BaseX but i...

1 20yrs

rwyoung

1 20yrs rwyoung

Weird problem in Xilinx WebPack ISE PACE 7.1SP4

Hi, I've tried to assign pins in PACE for a verilog module like this (I selected a spartan 3 fg456 package): module tes...

0 20yrs

fpgagrp

0 20yrs fpgagrp

RLDRAM-II controller - Read problem

I am currently designing an RLDRAM-II controller in a Xilinx Virtex-II Pro with the following specifications: Device =...

1 20yrs

ediesen

1 20yrs ediesen

Xilinx/Linux: sch2vhdl not working very hard

Hi everyone, Now that I've got the Xilinx Web-tools running reasonably well under Linux, I'm noticing that sch2vhld, wh...

2 20yrs

p.boven

2 20yrs p.boven

for...generate loop with generics, constants (vhdl)

suppose I want calculate the log2(N) were N is an integer valued generic or constant parameter in my design, now, lets...

2 20yrs

wallge

2 20yrs wallge

Inferring design elements in ISE tool

I am using ISE tool for implementing my design.But i am facing a problem.In this tool it is written that some modules a...

2 20yrs

sk.sulabh

2 20yrs sk.sulabh

VHDL 2 dimension array

Hi, I am just beginner of VHDL. I want to define a 2 dimensional input variable in entity. I think the syntax is someth...

4 20yrs

eehobbyist

4 20yrs eehobbyist

Synthesis with Icarus Verilog

I really like the idea of using Icarus Verilog as a Synthesis tool in our FPGA flow. I have only used it with a few sma...

0 20yrs

chris

0 20yrs chris

More than one embedded system in ISE

Only one source of type 'XPS FILE' is allowed in a project. Why can't I add more than one system.xmp file to ISE? I nee...

3 20yrs

francis.st-pierre

3 20yrs francis.st-pierre

ISE does not initialize the bitstream of a EDK project

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I...

5 20yrs

NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM

5 20yrs NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM

Virtex-4 FX20 PPC405 Startup Issue

Hello, I am looking for some help with a particularily nasty problem I have run into, Out of our 10 prototype Virtex-4-...

9 20yrs

chrisb7860

9 20yrs chrisb7860

reading bits using JBits 3.0

Hi, How does one read back specific bits using JBits 3.0? For example, if I want to read back the contents of the F LUT...

0 20yrs

sarnaths

0 20yrs sarnaths

fixed point dot product with log2(n) pipe stages in vhdl

I would like to write a parameterizeable component in vhdl that would do an N element fixed point dot product. I was wo...

1 20yrs

wallge

1 20yrs wallge

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