Field-Programmable Gate Arrays

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Avoiding meta stability?

Is the following a good way to avoid meta stability problems? The signal 'd' is synchronous to a1.8 MHz clock? At least...
51 comments posted 21yrs
posted by billbill
51 comments posted 21yrs posted by billbill

Problems in simulating EDK system

Hello! I want to debug my system generated in EDK, so I'm using ModelSim. I generated the simulation files and created...
0 comments posted 21yrs
posted by mvetromille
0 comments posted 21yrs posted by mvetromille

vhdl question

please someone let me know the effects of having "ibuf_lvcmos33" for each input , "obuf_lvcmos33" for each output and "...
12 comments posted 21yrs
posted by manusha
12 comments posted 21yrs posted by manusha

going backwards, Xilinx ISE 7.1 to ISE 6.3

I own and use Xilinx ISE 7.1 BaseX and to develop Spartan-3 code. I have a client who owns and uses ISE 6.3 BaseX but i...
1 comments posted 21yrs
posted by rwyoung
1 comments posted 21yrs posted by rwyoung

Weird problem in Xilinx WebPack ISE PACE 7.1SP4

Hi, I've tried to assign pins in PACE for a verilog module like this (I selected a spartan 3 fg456 package): module tes...
0 comments posted 21yrs
posted by fpgagrp
0 comments posted 21yrs posted by fpgagrp

RLDRAM-II controller - Read problem

I am currently designing an RLDRAM-II controller in a Xilinx Virtex-II Pro with the following specifications: Device =...
1 comments posted 21yrs
posted by ediesen
1 comments posted 21yrs posted by ediesen

Xilinx/Linux: sch2vhdl not working very hard

Hi everyone, Now that I've got the Xilinx Web-tools running reasonably well under Linux, I'm noticing that sch2vhld, wh...
2 comments posted 21yrs
posted by p.boven
2 comments posted 21yrs posted by p.boven

Inferring design elements in ISE tool

I am using ISE tool for implementing my design.But i am facing a problem.In this tool it is written that some modules a...
2 comments posted 21yrs
posted by sk.sulabh
2 comments posted 21yrs posted by sk.sulabh

VHDL 2 dimension array

Hi, I am just beginner of VHDL. I want to define a 2 dimensional input variable in entity. I think the syntax is someth...
4 comments posted 21yrs
posted by eehobbyist
4 comments posted 21yrs posted by eehobbyist

Synthesis with Icarus Verilog

I really like the idea of using Icarus Verilog as a Synthesis tool in our FPGA flow. I have only used it with a few sma...
0 comments posted 21yrs
posted by chris
0 comments posted 21yrs posted by chris

More than one embedded system in ISE

Only one source of type 'XPS FILE' is allowed in a project. Why can't I add more than one system.xmp file to ISE? I nee...
3 comments posted 21yrs
posted by francis.st-pierre
3 comments posted 21yrs posted by francis.st-pierre

ISE does not initialize the bitstream of a EDK project

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I...
5 comments posted 21yrs
posted by NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM
5 comments posted 21yrs posted by NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM

Virtex-4 FX20 PPC405 Startup Issue

Hello, I am looking for some help with a particularily nasty problem I have run into, Out of our 10 prototype Virtex-4-...
9 comments posted 21yrs
posted by chrisb7860
9 comments posted 21yrs posted by chrisb7860

reading bits using JBits 3.0

Hi, How does one read back specific bits using JBits 3.0? For example, if I want to read back the contents of the F LUT...
0 comments posted 21yrs
posted by sarnaths
0 comments posted 21yrs posted by sarnaths