Good morning,
I had a design wich was working fine in Libero 6.0 SP3 (Synplify
7.51A). I made an upgrade to Libero 6.2 SP2 (Synplify 8.1A). When I open the project the conversion works fine. Without changing anything to the vhdl files or viewdraw schematic file I redo the synthesis with Synplify. It seems to work without problem. I then open Designer. I get the following error message: Error: ERROR in SECTION GLOBAL_CLOCKS near line 17 :: DCF#023: Invalid pin Z_1I478:PAD. Pin is Ignored Warning: The constraint data (DCF) has unavailable net/pin references. The invalid constraints will be removed. I did not change anything to the clock pins! I prevent Synplify to use automatically all clock pins (HCLK, CLKA and CLKB) for all the clocks it finds in the design by adding two attribute lines (syn_noclockbuf...) in the vhd file created by viewdraw. And I use a CLKBUF in viewdraw to be allowed to set my clock signal on the CLKA pin. I am almost certain the problem comes from Synplify because if I do exactly the same steps but without redoing the synthesis, that is opening Designer directly after the conversion of the project then I get not error during the layout. Is there maybe an option in Synplify I have to change?
Thank you very much,
Marie