Hallo, I have made a clock divider using a counter connected to master clock and a comparator.
The comparator has a clock enable to avoid "gating-clock".
Now my trouble. I have connected some logic blocks to the new clock, but in this way it has high load and delay.
The warning message:
WARNING:Route - CLK
may have excessive skew because 3 NON-CLK pins
failed to route using a CLK template.
This peripheral is a part of a small micrcontroller based on microblaze.
What could I do to solve this trouble?
Many Thanks in advance