High Load

"Marco" schrieb im Newsbeitrag news:dhu289$tce$ snipped-for-privacy@news.ngi.it...

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1) you should connect ALL clk inputs to master clock (not the new clock) and use clock enables 2) why do you reinvent the wheel? the opb_spi core is provided by xilinx for free! 3) SPI is easier to implement as FSL peripheral :) 4) in most cases the GPIO bitbanged SPI is fastest to implement, and takes no resources (except gpio pins) sure takes some sw overhead

antti

Where possible I have made as you told. But there are some blocks, where I can't. In example, I must send a 1 MHz clock to a FPGA pin, 2 slave select for and ADC and a DAC... etc...

Yes, but it supports only 8 bit peripheral. I contacted Xilinx support and they told me that 16 bit peripheral are not still supported. In my project there are 2 16-bit peripheral, an ADC and a DAC.

I could try.

I have tried using a BUFG, and I think it could be a work around.

I would know if there are other solution when load is high.

Marco

Firstly.. a 16-bit spi peripheral is just done with two spi transactions.

Second.. don't use gated clocks.

Third.. see two (can't repeat this often enough).

Forth.. use a divide by two with a clock enable to generate the SPI clock. It will clean up all your problems. including sending on rising edge, receiving on falling edge. The only down side is it takes twice as long... so you wait 8 'busy_waits' instead of 4 .. usually it doesn't cause a problem.

Simon

and

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takes

I tried in the past, and it didn't work. I must send a clock enable to the ADC, wait for 5 clock cycle and then receive 16bit. When I receive 2 "packets" of 8 bit I loose some bits between the first and the second packet. The only way is to receive a packet of 16 bit sequentially.

I always have used FF with clock enable, but the clock enable now has high load (8-10 from report of XST synthesis).

Here my trouble... I would avoid high load to clock enable

I think you're talking about a dcm. I can't because the max freq. supported by ADC is 2.9 MHz...

In the past I tried with divide by 32 to obtain a freq. of about 1,5 MHz

Many Thanks for your answer and sorry to everyone for my bad english.

Marco

The warning talked about "3 NON-CLK pins" .. that's a dead giveaway for a gated clock somewhere or using a signal which isn't a clock.... or using a clock in a non-clock way. I would look at the circuit hard.

You might find a good option is to use a couple of SLR16's as counters for your SPI. each can replace a number of 'loads' with a single one.

Another option is to duplicate the clock for your SPI.. I am guessing that you are creating a clock from a system clock .. and then using it to clock both the IO pins and the logic. One solution is to duplicate the clock generator, the other is to ONLY use the system clock. use a gate to latch the incoming data which is generated in parallel to the clock not from the clock.

i.e. spi_clock : process (rst, clk) is begin if (rst = '1') then spi_clk ADC, wait for 5 clock cycle and then receive 16bit. When I receive 2

clock.

supported

4

The clock divider has 2 outputs: a 50% duty cycle and a pulse at the last count of counter. I have connected 3 state machine to the pulse. Every machine and the other block are faliing edge sensitive. I have made the counter and the comparator with core generator.

Seems a great idea, could you explain, please?

I will try it as soon as possible.

Many and many thanks for your precious help. Marco

I have finally found the trouble. I create a new thread to discuss on it.

Many Thanks Marco