Field-Programmable Gate Arrays

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I have received a job offer

Hallo, I would have a suggestion about. The job consist in: developing a microprocessor based system for data acquisiti...
7 comments posted 20yrs
posted by marcotoschi
7 comments posted 20yrs posted by marcotoschi

XC2VP125

The mighty P125. It's on datasheets from 2002, but it's not on the website anymore. Anyone I've asked about it has told...
2 comments posted 20yrs
posted by robin.bruce
2 comments posted 20yrs posted by robin.bruce

Using inout ports in VHDL

Hello, I'm trying to implement a bidirectional bus. I've declared the port as inout std_logic_vector, and the simulatio...
3 comments posted 20yrs
posted by ncunha
3 comments posted 20yrs posted by ncunha

LWIP on microblaze socket limit to 2

I have implemented the lwip2.00a in the edk. Even though I specified the number of connections to be five, I can only h...
0 comments posted 20yrs
posted by
0 comments posted 20yrs posted by

using Spartan3 DCM in ActiveHDL

is there a way to use spartan3 dcm in active-hdl??
0 comments posted 20yrs
posted by kerby.martino
0 comments posted 20yrs posted by kerby.martino

Xilinx trouble opening ml40x_emb_ref_xx

Hello group, First of all I have tried to download the reference design for the ML403 twice today with no luck. The dow...
4 comments posted 20yrs
posted by bradsmallridge
4 comments posted 20yrs posted by bradsmallridge

crc code using vhdl found , few questions on it!!!

Hello everyone, This link http://www.easics.be/webtools/crctool has the software to generate the vhdl code for the crc...
1 comments posted 20yrs
posted by achiluka
1 comments posted 20yrs posted by achiluka

FPGA : PCI core needed

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI...
7 comments posted 20yrs
posted by sa0les1
7 comments posted 20yrs posted by sa0les1

Newbie. Clocks.

My head is spinning.. One should only use one of the edges in a clock domain, right But if I have a memory read set up a...
7 comments posted 20yrs
posted by miti0200
7 comments posted 20yrs posted by miti0200

clock detection

Hi I need advice to build a very small firmware which will detect if clock signal is active or not Indeed, My FPGA (V2P...
6 comments posted 20yrs
posted by sebastien.coquet
6 comments posted 20yrs posted by sebastien.coquet

ChipScope on ML401 kit

I have problems getting ChipScope to work with the Xilinx ML401 kit. I have been trying to find a solution at "Xilinx a...
2 comments posted 20yrs
posted by raybakk
2 comments posted 20yrs posted by raybakk

differential clock in EDK

Hi all, I'm doing a project on a Virtex-2P-40. The FPGA is fed with a differential clock pair and I am not quite sure h...
6 comments posted 20yrs
posted by xjohbex
6 comments posted 20yrs posted by xjohbex

FPGA : PCI-CORE

Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device want to port the same design to spartan-3e25...
16 comments posted 20yrs
posted by pbijoy
16 comments posted 20yrs posted by pbijoy