Latest threads in Field-Programmable Gate Arrays

Spartan IIE VHDL inout port bidirectional bus problem.

Hi, I am trying to use a bidirectional bus, declared as inout in my vhdl code. When running on FPGA eveything works, ex...

1 21yrs

liaobojie

1 21yrs liaobojie

Lead To Lead Free ROHS help?

If you need some ROHS help I work as a component engineer out in San Diego county California. I have a service that hel...

0 21yrs

dolbowent

0 21yrs dolbowent

can ethereal detect an ethernet packet for which crc is wrong

Hello everyone, I am sending an ethernet packet(64 bytes) from the fpga to the PC in order to test the ETHERNET PHY chi...

9 21yrs

achiluka

9 21yrs achiluka

Virtex4 temperature-sensing feature... does it work?

Hello guys, Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the results were all right, what external...

5 21yrs

delete

5 21yrs delete

Xilinx V2P Speed Grades

Hi there, Has anyone of you experience with the speed gain on a Virtex2Pro when going from -5 to -6? I mean, the differ...

0 21yrs

sheinzle

0 21yrs sheinzle

Thank-you Xilinx!

The Platform Flash configuration devices are finally available on the online store! -Eli

1 21yrs

emh203

1 21yrs emh203

Simulating Cyclone II PLL

Hi, I've got a problem which has me stumped. We've got a design that actually *runs* in real hardware. I'm in the proce...

2 21yrs

markm

2 21yrs markm

Xilinx ML403 Error 1 LED

Hi I just got two ML403 boards. 2nd board when turned on with the cf card in the Error 1 LED is displayed. There is no...

4 21yrs

question on sw tools for xilnx FPGA

Hi, I just started to learn FPGA (xilinx) with ISE 7.1 and ModelSim XE III. If I want to use microblaze or other IP core...

2 21yrs

ppirrip

2 21yrs ppirrip

Quartus II Simulation

Hello, I am trying to use .vwf files to simulate some designs (I'm not doing this out of choice...being forced to do it...

2 21yrs

saurster

2 21yrs saurster

Integrator

Hallo, How may I realize an integrator into a FPGA? Many Thanks Marco

2 21yrs

marcotoschi

2 21yrs marcotoschi

[xst]:clk information question

Hey, i made a design for a LVDS input (with some tweaks) and the design is working but i found this info warning in the...

0 21yrs

tim.verstraete

0 21yrs tim.verstraete

Memory usage and ISE

Hi All, I am trying to P&R an XC2V8000 with a large number of MCP constraints on a 2GB (+2GB swap, /3GB switch in boot....

1 21yrs

hans64

1 21yrs hans64

SystemACE parts wanted

Hi, Does anyone have any SystemACE parts for sale (upto 15 pieces) or know any distributor who has some in stock? Cheers...

7 21yrs

jon

7 21yrs jon

array type implementable in ISE?

hi In my implementation, top entity has some pins with array type in VHDL. It is strange that ISE does not map / place a...

1 21yrs

JEmoderatz

1 21yrs JEmoderatz

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