Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device
want to port the same design to spartan-3e250 device.
have changed the pin assignment but was getting the following error during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too,
how can i port the design to another device, may i get some direction to proceed in this regard
When you buy the Core, you normally get a user Id and a passwd to access the private section in Xilinx website so that you can change the UCF online, I think?
You can also contact the guy who sold you the core in the first place.
Regards,
-- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O)
Hi First of all i would like to Thank You for your immediate response.
The problem i am facing is different, we have got a PCI core from xilinx for demo purpose with a ucf and for spartan-3 200 device.
Now we want to try the same in the spartan-3e-250 device due to some cost consideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device.
This is my real problem, i am trying all my option in my hand, but i am not familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me.
"bijoy" schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...
for demo purpose with a ucf and for spartan-3 200 device.
consideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device.
not familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me.
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that e-book includes ALL instructions how to get an PCI design up and running. the PCI core used there is VERY simple and usually works out of box, you just assign PCI IO pins and constraint on PCI clock nothing else. I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards.
its not a solution for your problem, but its an EASY way to test an existing PCI FPGA board.
"Nial Stewart" schrieb im Newsbeitrag news:4368d700$0$23295$ snipped-for-privacy@news.zen.co.uk...
boards.
YES. it also includes a LPT connected logic analyzer (uses BRAM's). so original software written for LPT connected logic analyzer does run on the PCI board.
the PCI LPT is 'Lava PCI LPT' it is recognized by Windows XP nativly no extra driver just regular LPT (with 16 base address !!!) any software that can talk to LPT can talk to the PCI core, and whatever is connected to the virtual LPT wires.
I am using the same PCI-LPT with xilinx cable III emulation in MAX2 starterkit as PCI Xlinx Cable III :)
Antti
PS Nial, I have verified the PCI part of the cores on your cyclone board it worked. the LPT stuff is just later mods not verified on your cyclone board but I am confident it should work as well.
It shouldn't be tough to get things running. If you look at the pad report generated during place & route, you'll find the banks and what the tool believes the VCCO should be for those banks. You may have an I/O from somewhere else in your design that wants to share a bank with the PCI pins but doesn't use the 3.3V.
The Spartan-3E has a bunch of input-only pins that you need to keep track of since most of the PCI signals are I/O. Also, your config file has a bit that will put the "PCI_LOGIC" block back into use; the Spartan-3 dropped the feature but the Spartan-3E brought it back. You can look at FPGA Editor to see the expected placement of the I/Os relative to the PCI_LOGIC block assuming you're not using the free Xilinx tools (which don't have the FPGA Editor if I recall correctly).
"John_H" schrieb im Newsbeitrag news:r16af.26$ snipped-for-privacy@news-west.eli.net...
Hi John,
the the PCI_LOGIC is undocumented FPGA primitive do you happen to have addtional info about it? is useable in non xilinx design by using hard macro wrapper around it or by other means?
I have no documentation on the functionality of the block. I only know that it's included or excluded in the Xilinx PCI cores through the PCI .cfg file. Others have wondered about explicit functionality before - you might find something with Google. Generally, it's used to provide clock enables to the data lines combinatorially based on the PCI interface IRDY and TRDY (and other core) signals since these have the most stressed timing in PCI.
My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. While the current release of the BDS XPCI PCI IP core (Ver. 1.0.0) doesn't come with a constraint file for Spartan-3 or Spartan-3E, we have done Post Place & Route simulation of BDS XPCI PCI IP core in Spartan-3, and has functioned properly. Therefore, we should be able to port it to Spartan-3E relatively easily, and we can also specifically create a UCF constraint file for the particular Spartan-3E part you have. The BDS XPCI32 PCI IP core commercial perpetual license version normally costs $3,000 for domestic customers/$3,600 for foreign customers, but as an introductory pricing, we will offer it for $2,000 for domestic customers/$2,400 for foreign customers. Only the first few customers will get the introductory pricing, so if you are interested, we recommend that you contact us right away. For other interested ordinary FPGA users, we offer BDS XPCI32 PCI IP core is available for as little as $100 for non-commercial, non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200. Since the pricing starts at only $100, it is ideal for HDL learners, FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or student graduation projects. BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which allows the user to simulate the design extensively on HDL simulators before firing up the FPGA. ModelSim including ModelSim XE is supported by BDS XPCI PCI IP core, and the next release of BDS XPCI PCI IP core will support a $50 Verilog HDL simulator called Veritak by Sugawara Systems
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as a low cost alternative to ModelSim XE. (Current version doesn't function properly in Veritak, but the problem has been fixed.) VHDL support is currently poor, but VHDL porting of reference designs and PCI testbench should be available in a month. (Porting has been taking a little longer than expected.) BDS XPCI PCI IP core officially supports the following PCI boards.
- Insight Electronics Spartan-II 200 PCI Development Kit
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BDS XPCI PCI IP core "unofficially" supports the following PCI boards.
- Avnet Xilinx Spartan-3 Evaluation Kit
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- Enterpoint Broaddown2 Development Board
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So with BDS XPCI PCI IP core, almost anyone can make their own PCI device for about $450 to $550. ($300 to $400 for the board + $100 for BDS XPCI32 PCI IP core + $50 for Veritak.) For commercial users who want to modify a Xilinx LogiCORE PCI or want to convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL. For more information, visit Brace Design Solutions website at
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Kevin Brace
bijoy wrote:
place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too,
proceed in this regard
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
We have figured out how to use PCILOGIC in our Xilinx (TM) LogiCORE (TM) PCI compatible PCI IP core called BDS XPCI PCI IP core. It basically gives very fast routing for IOB Output FF's CE (Clock Enable) input, but as many already know, it is supported by Virtex, Virtex-E, Spartan-II, and Spartan-IIE only. Xilinx dropped the support of PCILOGIC starting in Virtex-II.
Kevin Brace
John_H wrote:
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
It is fairly easy to find out what the macro does and to use it; at least this procedure used to work;) I have not tried it with a recent version of the Xilinx tools.
First of all, look at the macro in with FPGA editor. It will show the name of the module, and the name of the pins. Create a new design and instantiate just the macro, as a black box, and connect the inputs and outputs to FPGA pins. Generate the FPGA; the tools understand the macro. Run ngd2vhdl (or ngd2ver). The result should be an HDL model of the macro, which you can now use for simulation.
I stand corrected. You are right that Xilinx did get PCILOGIC back in Spartan-3E. I was sort of skeptical because I always thought that Xilinx no longer needed PCILOGIC because FPGAs have gotten so much faster, but I still ran the following Verilog design instantiating PCILOGIC.
------------------ Command Line : C:/Xilinx/bin/nt/map.exe -ise c:\pcilogic\spartan_3e\PCILOGIC.ise -intstyle ise -p xc3s250e-pq208-4
-cm area -pr b -k 4 -c 100 -o PCILOGIC_Test_map.ncd PCILOGIC_Test.ngd PCILOGIC_Test.pcf Target Device : xc3s250e Target Package : pq208 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.26.6.4 $ Mapped Date : Fri Nov 04 09:53:03 2005
Design Summary
-------------- Number of errors: 0 Number of warnings: 2 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 6 out of 158 3% Number of PCILOGICSEs: 1 out of 2 50%
Total equivalent gate count for design: 0 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 112 MB
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing.
Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.
-------------------- WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.
Section 3 - Informational
------------------------- INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
------------------------ Guide not run on this design.
Section 9 - Area Group Summary
------------------------------ No area groups were found in this design.
Section 10 - Modular Design Summary
----------------------------------- Modular Design not used for this design.
Section 11 - Timing Report
-------------------------- This design was not run using timing mode.
Section 12 - Configuration String Details
-------------------------- Use the "-detail" map option to print out Configuration Strings
Section 13 - Additional Device Resource Counts
---------------------------------------------- Number of JTAG Gates for IOBs = 6 Number of Equivalent Gates for Design = 0 Number of RPM Macros = 0 Number of Hard Macros = 0 STARTUP_SPARTAN3E = 0 PCILOGICSE = 1 MULT18X18SIO = 0 DCIRESETs = 0 CAPTUREs = 0 BSCANs = 0 STARTUPs = 0 DCMs = 0 GCLKs = 0 ICAPs = 0
18X18 Multipliers = 0 Block RAMs = 0 IOB Master Pads = 0 IOB Slave Pads = 0 IOB ODDR2 = 0 IOB IDDR2 = 0 IOB Regular Flip Flops not driven by LUTs = 0 IOB Regular Flip Flops = 0 IOB Latches not driven by LUTs = 0 IOB Latches = 0 Unbonded IOBs = 0 Bonded IOBs = 6 XORs = 0 CARRY_INITs = 0 CARRY_SKIPs = 0 CARRY_MUXes = 0 Shift Registers = 0 Static Shift Registers = 0 Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0 Dual Port RAMs = 0 MUXFs = 0 MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 0
4 input LUTs = 0 Slice Latches not driven by LUTs = 0 Slice Latches = 0 Slice Flip Flops not driven by LUTs = 0 Slice Flip Flops = 0 SliceMs = 0 SliceLs = 0 Slices = 0 F6 Muxes = 0 F5 Muxes = 0 F8 Muxes = 0 F7 Muxes = 0 Number of LUT signals with 4 loads = 0 Number of LUT signals with 3 loads = 0 Number of LUT signals with 2 loads = 0 Number of LUT signals with 1 load = 0 NGM Average fanout of LUT = -1.#J NGM Maximum fanout of LUT = 0 NGM Average fanin for LUT = -1.#IND ________________________
I guess PCILOGIC is now called PCILOGICSE. (PCILOGIC Second Edition? PCILOGIC S(partan-3)E?)
Kevin Brace
John_H wrote:
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
How did you create a PCI core compatible with the Lava drivers? Did you develop or reverse engineer the Lava PCI bridge? Or did you use the Lava Xilinx FPGA in a design?
I'd really be interested to hear how you got this working.
"Ram" schrieb im Newsbeitrag news:1n1bf.4575$ snipped-for-privacy@tornado.socal.rr.com...
Hi Ram,
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its all explained there :)
but really there was no need to RE anything. I do not do RE unless there is a real need in that. The change of an exisiting PCI IP core to look like Lava LPT card was maybe 10 changed HDL code lines in total. Why do extra work? I am rather prefer to be lazy in creative way :)
You can either choose to change those 10 lines of source code, or buy the E-book for 10 USD.
Ah - as special agreement with Enterpoint Ltd.
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this E-Book and 'book resources' are free for ALL owners of the RaggedStone-1 Spartan-3 PCI FPGA Board. And yes ready to use .BIT and .MCS files for this board are also supplied with the E.book.
or if you want to say the penny and do it all by yourself then just look at PCI specs for the LPT class codes, and choose some VID/PID that works. Thats it.
BTW I have never owned or hold in my hands any Lava PCI cards. I just adjusted the PCI config space so that the PCI card gets configured by WindowsXP 'silently' without the need of additional drivers.
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