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crc code using vhdl found , few questions on it!!!

Hello everyone, This link

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has the software to generate the vhdl code for the crc 32 polynomial. But the data bus width is only upto 256 bits.

In the below code, crc is computed on only 4 bits of data. But i need to compute the crc on destination address, source address, length, data. which could be 72 nibbles or more. My assumption, is that in each clock cycle i send 4 bits to this combinational logic(logic in the attachment) and the previous new crc becomes C in every clock cycle.So after i am done sending all the data, the final new crc will be the actual crc [32 bits] which is being appended to the end of the frame. Is this assumption right? I will change the variable assignment to the signal assignment though.

NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30);

NewCRC(1) := D(7) xor D(6) xor D(1) xor D(0) xor C(24) xor C(25) xor C(30) xor C(31);

NewCRC(2) := D(7) xor D(6) xor D(2) xor D(1) xor D(0) xor C(24) xor C(25) xor C(26) xor C(30) xor C(31);

NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(25) xor C(26) xor C(27) xor C(31);

NewCRC(4) := D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(24) xor C(26) xor C(27) xor C(28) xor C(30);

NewCRC(5) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(1) xor D(0) xor C(24) xor C(25) xor C(27) xor C(28) xor C(29) xor C(30) xor C(31);

NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor C(25) xor C(26) xor C(28) xor C(29) xor C(30) xor C(31);

NewCRC(7) := D(7) xor D(5) xor D(3) xor D(2) xor D(0) xor C(24) xor C(26) xor C(27) xor C(29) xor C(31);

NewCRC(8) := D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor C(24) xor C(25) xor C(27) xor C(28);

NewCRC(9) := D(5) xor D(4) xor D(2) xor D(1) xor C(1) xor C(25) xor C(26) xor C(28) xor C(29);

NewCRC(10) := D(5) xor D(3) xor D(2) xor D(0) xor C(2) xor C(24) xor C(26) xor C(27) xor C(29);

NewCRC(11) := D(4) xor D(3) xor D(1) xor D(0) xor C(3) xor C(4) xor C(25) xor C(27) xor C(28);

NewCRC(12) := D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor C(4) xor C(24) xor C(25) xor C(26) xor C(28) xor C(29) xor C(30);

NewCRC(13) := D(7) xor D(6) xor D(5) xor D(3) xor D(2) xor D(1) xor C(5) xor C(25) xor C(26) xor C(27) xor C(29) xor C(30) xor C(31);

NewCRC(14) := D(7) xor D(6) xor D(4) xor D(3) xor D(2) xor C(6) xor C(26) xor C(27) xor C(28) xor C(30) xor C(31);

NewCRC(15) := D(7) xor D(5) xor D(4) xor D(3) xor C(7) xor C(27) xor C(28) xor C(29) xor C(31);

NewCRC(16) := D(5) xor D(4) xor D(0) xor C(8) xor C(24) xor C(28) xor C(29);

NewCRC(17) := D(6) xor D(5) xor D(1) xor C(9) xor C(25) xor C(29) xor C(30);

NewCRC(18) := D(7) xor D(6) xor D(2) xor C(10) xor C(26) xor C(30) xor C(31);

NewCRC(19) := D(7) xor D(3) xor C(11) xor C(27) xor C(31);

NewCRC(20) := D(4) xor C(12) xor C(28);

NewCRC(21) := D(5) xor C(13) xor C(29);

NewCRC(22) := D(0) xor C(14) xor C(24);

NewCRC(23) := D(6) xor D(1) xor D(0) xor C(15) xor C(24) xor C(25) xor C(30);

NewCRC(24) := D(7) xor D(2) xor D(1) xor C(16) xor C(25) xor C(26) xor C(31);

NewCRC(25) := D(3) xor D(2) xor C(17) xor C(26) xor C(27);

NewCRC(26) := D(6) xor D(4) xor D(3) xor D(0) xor C(18) xor C(24) xor C(27) xor C(28) xor C(30);

NewCRC(27) := D(7) xor D(5) xor D(4) xor D(1) xor C(19) xor C(25) xor C(28) xor C(29) xor C(31);

NewCRC(28) := D(6) xor D(5) xor D(2) xor C(20) xor C(26) xor C(29) xor C(30);

NewCRC(29) := D(7) xor D(6) xor D(3) xor C(21) xor C(27) xor C(30) xor C(31);

NewCRC(30) := D(7) xor D(4) xor C(22) xor C(28) xor C(31);

NewCRC(31) := D(5) xor C(23) xor C(29);

Reply to
ashwin
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You have found the page that many of us have found useful as a starting point. Typically for regression tests, you may want to set the width to

1 bit, and supply your data to the routine 1 bit at a time. This is the simplest form of CRC hardware, and it is fairly easy to see how it maps to the CRC polynomial. The downside is it computes CRC at only 1 bit per clock cycle. At 10 MBits per second (10BaseT ethernet) this is no big problem, but at 1000 Mbits per second (Gigabit ethernet) this would be pretty much impossible to achieve (only 1 ns per cycle).

The solution is to calculate CRC in parallel. The easics crctool lets you choose any width you like from 1 bit to 256 bits. You trade off complexity for speed, with the complexity growing aproximately linearly from 1 bit to 32 bits, then pretty much leveling off from 33 bits to

256 bits.

To use the widths other than 1 bit, you need to look at the bit serial form of your data, and take it N bits at a time and feed it to the parallel CRC circuit you have chosen. Due to the byte nature of the data, using an "8 bit at a time" CRC circuit is a fairly natural choice.

OK, 4 bits at a time is good too. Has to run at 1/4 of the bit rate or 2 times the byte rate.

This works regardless of the packet length. You just take the data and stream it into the CRC circuit at the appropriate rate and width.

Exactly right.

Go back and re-read my previous answer to you. The CRC is complemented then bit reversed to become the FCS that is appended to the end of the frame.

Pretty much.

Philip

Reply to
Philip Freidin

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