differential clock in EDK

"Johan Bernspång" schrieb im Newsbeitrag news:dka7nj$l7t$ snipped-for-privacy@mercur.foi.se...

if the clock goes to DCM you need to make sure the DCM wrapper does not include a bufg in the clock input, then you just create a user logic with lvds clock buf. thats it. must work.

antti

I think you should change the synthesis option /Xilinx specific options/add I/O buffers to false

I have had the same problem! Seems that there should be a way in the User Constraints file to specify this!

-Eli

Well, I thought so too. (No additional bufg is included in the DCM wrapper). But EDK is adding buffers during the synthesis on all global I/Os regardless on what is defined in the UCF file. (Zara: I can't find where in EDK I set the I/O-buffer option you mentioned, and I still want all other global I/Os to have buffers).

Examing the system.vhd file gives the following information. If I define the ports refclk_p and refclk_n as clock signals in the MHS file (SIGIS = CLK) the synthesis is connecting the ports to BUFGPs before connecting the signals to my IBUFGDS-core. When the SIGIS = CLK is omitted the ports are connected to ordinary IBUFs.

In ISE this issue isn't even an issue, there should be a way to work this out in EDK as well. The Xilinx dev boards ML40x have connectors for external differential clock inputs...it must work somehow.

Regards

Here is I handle differential clock input with BSB/EDK. Xilinx Answer Record 19539 discusses the general strategy which uses a pcore that converts from differential inputs to single net inside the FPGA. Have a single ended clock in the XBD and generate the design. Change the following in the generated MHS: PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK ... to: PORT diff_sys_clk_n_pin = diff_sys_clk_n, DIR = INPUT PORT diff_sys_clk_p_pin = diff_sys_clk_p, DIR = INPUT ... And add the following pcore instantiation: BEGIN DIFF_INPUT_BUF PARAMETER INSTANCE = DIFF_INPUT_BUF_0 PARAMETER HW_VER = 1.00.a PARAMETER INPUT_BUS_WIDTH = 1 PORT DIFF_INPUT_P = diff_sys_clk_p PORT DIFF_INPUT_N = diff_sys_clk_n PORT SINGLE_ENDED_INPUT = dcm_clk_s END Then modify the UCF to duplicate the single ended LOC and constraints to the second differential pin. I've been doing this with the XUPV2P board for several months and haven't had any issues. I've already made an enchancement request to the Xilinx EDK team to natively support this. Would anyone else find such support useful?

Paul

Johan Bernspång wrote:

Thanks Paul, your comment put me on the right track. The answer record

The only thing I had to add to my design was IOB_STATE=BUF after the two differential ports in the MPD-file. The design is working fine now.

regards