Newbie. Clocks.

My head is spinning.. One should only use one of the edges in a clock domain, right

But if I have a memory read set up at "posedge clk"

verilog ex

always @(posedge clk

ram_adress

Reply to
mice
Loading thread data ...

Keep away from gated clocks until you know how a clocked system works. I would recommend to start at

formatting link
for an introduction.

-- Brian

mice wrote:

Reply to
Brian Dam Pedersen

Dear Rodents, I sold my soul long ago, and even then it wasn't kind! However, I'll try and help. OK, it's important your clock has very little skew. This means it arrives at all the FFs at the same time. Fogs provide a special low skew feature for this purpose. Look for BUFG on Xilinx's website. Also, it's important that your FFs have short hold times. You'll find FPGAs' FFs are of this type. This means you can use the rising edge of your clock to clock all the FFs in your design, without getting race conditions and the like. The delay from one FF to the next is enough to meet the hold condition, provide your skew is low enough. If your clock is too fast, or the delays too long, you won't meet the setup condition, but that's another subject... HTH, Syms.

Reply to
Symon

Fogs = FPGAs. Bloody spell-checker.

Reply to
Symon

Memory Question: The memory data output will be delayed by one clock cycle positive edge from the address input. Your code would look like always @(posedge clk) begin ram_address

Reply to
Kunal Shenoy

An earlier incarnation of Word used to replace my former boss's name, Geoff, with "Goof." This was not only unfair but potentially career-limiting.

The only thing worse than the spell checker is the grammar checker.

Bob Perlman Cambrian Design Works

Reply to
Bob Perlman

The question you're asking is, "when is the read data word available?" If it's a synchronous RAM, then your answer has to be "on the next rising edge of the clock." If it's an asynchronous RAM, then the answer is, "do a timing analysis," but the usual method is to choose a clock frequency such that the read data word is available on the next rising clock edge.

It's actually the simplest way to do it. Of course you could read the data (from an async RAM) on the falling edge of the clock, but you have to ensure that the data are valid at that time.

In a modern FPGA, use one of the built-in clock divider/multiplier blocks. They're free and they work.

-a

Reply to
Andy Peters

You're all too kind

The reason why I'm asking these starter-questions is that my read-onl

SPI sometime misses a byte. And it's using both flanks of a clock It worked ok without so much other stuff in there, but after a whil it started t act strange I've, almost, built a complete SoC (CPU,SPI,Mem-Manager and GPU) an there is so muc going on in here that I really had no clue where to start looking fo the SPI problem As a test I now let the part that handled the SPI run on a 12.5Mh clock instead of a 25Mh and now it's stable again

If I'd had a timing report generated that would have told me th

delays for the relevan path's I might have discovered this sooner. Alas, I've started to rea how th constraints works This probably isn't the "right" way to learn things, but I'd like t see results fas whenever I do something, which means missing basic "how it works stuff until problem pops up. Good thing I'm not building houses..

My todo list

- Learn Constraint

- Implement/learn DC

- Taking a bl**dy electronics cours

These new cheap "Fogs" are the coolest thing! Can't remember when

had this much fun before..

Thanks to you all

((mic

Reply to
mice

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.