Latest threads in Field-Programmable Gate Arrays

problem with timing simulation (clear explanation of problem)

Hi all, to be more clear about my problem with timing simulation after i implement it using xilinx it is creating one T...

1 20yrs

bachimanchi

1 20yrs bachimanchi

problem with timing simulation

Hi all, i am having a problem with timing simulation. i am getting proper outputs for functional simulation and post-sy...

0 20yrs

bachimanchi

0 20yrs bachimanchi

Xilinx V4 ISERDES problem

I am having trouble with the Xilinx ISERDES in Master/Slave configuration. I can get data from the first output registe...

2 20yrs

bradsmallridge

2 20yrs bradsmallridge

Is it legal to write an logical equation for a FPGA LUT in claims of a patent?

Hi, I am writing a patent application for FPGA and have no prior experiences with patent writing. I found that in Xilin...

14 20yrs

wtxwtx

14 20yrs wtxwtx

Synthesize: Error

Hi, if anyone could help me. I had declare real variable in vhdl and everything seems to be working after running simul...

4 20yrs

oceanfrea

4 20yrs oceanfrea

Spartan3E availability update

Hiho Spartan3E status: 1) Avnet has sold 400 (maybe a few hundred more) of their 69USD XC3S100E based starterkit, now t...

3 20yrs

antti

3 20yrs antti

Virtex 4 IDELAY implementation

Hi I'm currently doing some tests on an ML461 board, using IDELAY t shift in some DDR signals. I am shifting 80 signals...

2 20yrs

tky127

2 20yrs tky127

Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Calling all FPGA experts! I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter 6.0a simulator. The FPGA...

4 20yrs

chloe_music2003

4 20yrs chloe_music2003

FPGA : Decimation Filter Implementation

Hello I am trying to reverse engineer the decimation filter core provided by xilinx core-generator. My requirements are...

9 20yrs

pbijoy

9 20yrs pbijoy

Curious about FPGAs

Hi. I'm curious about exactly what sort of things are done with FPGAs. Is the main reason for their use the additional...

3 20yrs

clemenr

3 20yrs clemenr

Virtex-4 FX60 based products are already shipping now !

As of PLDA they are shipping __now__ their XpressFX board that has FX60 chip on board! Interesting though that there is...

10 20yrs

antti

10 20yrs antti

Quick question, how do I supply +-5V?

I have a large board which asks for three power supplies, +3V, +3.3V and +-5V. First two can be easily satisfied with t...

25 20yrs

Francis.invalid

25 20yrs Francis.invalid

Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)

I'm trying to build a simple ALU with an adder/subtracter unit and I need both carry and overflow outputs to set the ap...

27 20yrs

juendme

27 20yrs juendme

Any fpga tutorials online?

Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx ISE and vhdl to build some components and no...

5 20yrs

nordicelf

5 20yrs nordicelf

Quartus db issue

I was now searching for an error in my design for hours.... As a last try I removed the folder db in the quartus projec...

2 20yrs

mschoebe

2 20yrs mschoebe

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