Okashii schrieb:
Hi, First of all... Read the datasheets of the device family you are about to design for. They are available at the Xilinx homepage.
Second.. If you are working with the ISE ide (which comes with a fine tutorial) you must know that it chooses by default the smallest device of the selected fpga family. Just go and change your project properties to a larger device and/or a package with more pins. That's all.
have a nice synthesis
Eilert
Have a look at this Xilinx publication
John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan-3 Development Board.
Okashii wrote:
Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx ISE and vhdl to build some components and no matter what the size of component I keep getting "number of bonded iob" exceeded. Then after some observation I finally realized that its the size of bits of the ports of the top level component :P. May I know where I can find layman information on fpga online that explains what are "slices, slice flip-flops, LUT, IOB" and all these? Thanks in advance!
Hi Okashi,
I found the tutorial at XESS.COM very useful when I was just starting out. That was a year or so ago and things change. Seems like you are having trouble with pin IO counts, however, so you should go to the Xilinx site and look for there comparative data. Or just ask the group, we'll size it.
Brad Smallridge aivision.com
For most Xilinx families datasheets there is a page near the end of section that has an I/O count versus package table.
There is also information in Xcell which you can download here
John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development Board.
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