Field-Programmable Gate Arrays

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Which Phy transceiver for 10/100 ethernet?

Hallo, I should buy a phy transceiver for xilinx opb ethernet core. Which model dou you suggest? Many Thanks Marco
1 comments posted 20yrs
posted by marcotoschi
1 comments posted 20yrs posted by marcotoschi

Ethenet Multiplexers

Hi All, Can anyone please tell me about some good links or documents paprs etc. on Implementing Ethernet Multiplexers us...
6 comments posted 20yrs
posted by kedarpapte
6 comments posted 20yrs posted by kedarpapte

Xilinx LUT behavior question

If I change one input to a LUT, and leave the other three inputs unchanged, such that both the original and new output w...
10 comments posted 20yrs
posted by eric
10 comments posted 20yrs posted by eric

Supplier of Xilinx XC2V1000 or 2V250?

I think these parts may be obsolete. I can't find any suppliers in the USA. I need package type FG456. Does anyone know...
5 comments posted 20yrs
posted by anon
5 comments posted 20yrs posted by anon

Xilinx timing constraint problem

Dear all, I place a timing constraint on a pair of registers (from, to) either side of some logic. After I run the ISE...
2 comments posted 20yrs
posted by anon
2 comments posted 20yrs posted by anon

Xilinx EDK GPIO IP with FIFO function (input only)

Hi, i need to modify the GPIO IP (opb_gpio) (Xilinx EDK7.1) to work like a FIFO (only for input). The IPIF IP can ba con...
1 comments posted 20yrs
posted by m.bodenbach
1 comments posted 20yrs posted by m.bodenbach

Download old Quartus versions (4.0, 4.1)

Does anyone know if it's possible to download older versions of the Quartus web edition, such as 4.0 or 4.1? I'm inherit...
9 comments posted 20yrs
posted by cs_posting
9 comments posted 20yrs posted by cs_posting

systemC vs VHDL

hi everybody I'm learning two ways of describing a system .... Either by using systemC and the other way, VHDL ! What a...
8 comments posted 20yrs
posted by christophe.lucarz
8 comments posted 20yrs posted by christophe.lucarz

DSP vs FPGA

Hi every one, It seems that implementation of DSP algorithm In simulink is possible not only for TI DSPs but also XILIN...
1 comments posted 20yrs
posted by ar_kf
1 comments posted 20yrs posted by ar_kf

ISE Simulator not present in Linux?

Hi, I just succesfully installed ISE BaseX on Linux. All is OK. BUT the ISE simulator is not present in the list of avai...
10 comments posted 20yrs
posted by taileb.mehdi
10 comments posted 20yrs posted by taileb.mehdi

Clock problem? Altera Stratix-II ES and MP

Hi, all. This is Tomoya greeting from Japan. I would like to hear about Altera Stratix-II ES(engineering sample)/MP(mas...
2 comments posted 20yrs
posted by tkaku
2 comments posted 20yrs posted by tkaku

Q-bus or Unibus bus transactions in FPGA?

[Please do not mail me a copy of your followup] Has anyone implemented a Q-bus or Unibus bus interface logic in an FPGA...
12 comments posted 20yrs
posted by legalize+jeeves
12 comments posted 20yrs posted by legalize+jeeves