Latest threads in Field-Programmable Gate Arrays

Help : Code works in synthesizer (silos), but warnings w/ webpack

So I'm a newbie to DPL, though I'm experienced w/ microcontrollers. I wrote code for a CPLD (xilinx target, though it c...

5 20yrs

google

5 20yrs google

Ethenet Multiplexers

Hi All, Can anyone please tell me about some good links or documents paprs etc. on Implementing Ethernet Multiplexers us...

6 20yrs

kedarpapte

6 20yrs kedarpapte

Xilinx LUT behavior question

If I change one input to a LUT, and leave the other three inputs unchanged, such that both the original and new output w...

10 20yrs

eric

10 20yrs eric

Supplier of Xilinx XC2V1000 or 2V250?

I think these parts may be obsolete. I can't find any suppliers in the USA. I need package type FG456. Does anyone know...

5 20yrs

anon

5 20yrs anon

Xilinx timing constraint problem

Dear all, I place a timing constraint on a pair of registers (from, to) either side of some logic. After I run the ISE...

2 20yrs

anon

2 20yrs anon

Xilinx EDK GPIO IP with FIFO function (input only)

Hi, i need to modify the GPIO IP (opb_gpio) (Xilinx EDK7.1) to work like a FIFO (only for input). The IPIF IP can ba con...

1 20yrs

m.bodenbach

1 20yrs m.bodenbach

Download old Quartus versions (4.0, 4.1)

Does anyone know if it's possible to download older versions of the Quartus web edition, such as 4.0 or 4.1? I'm inherit...

9 20yrs

cs_posting

9 20yrs cs_posting

I have problem with schematic Webpack. Why can't 2 Bus on 1 Output?

Hello Sorry i write an understandig very bad english. I want make a projekt(Webpakc 7.1) with schematic and not VHDL !...

3 20yrs

enigmaolten-thomas

3 20yrs enigmaolten-thomas

systemC vs VHDL

hi everybody I'm learning two ways of describing a system .... Either by using systemC and the other way, VHDL ! What a...

8 20yrs

christophe.lucarz

8 20yrs christophe.lucarz

DSP vs FPGA

Hi every one, It seems that implementation of DSP algorithm In simulink is possible not only for TI DSPs but also XILIN...

1 20yrs

ar_kf

1 20yrs ar_kf

ISE Simulator not present in Linux?

Hi, I just succesfully installed ISE BaseX on Linux. All is OK. BUT the ISE simulator is not present in the list of avai...

10 20yrs

taileb.mehdi

10 20yrs taileb.mehdi

Clock problem? Altera Stratix-II ES and MP

Hi, all. This is Tomoya greeting from Japan. I would like to hear about Altera Stratix-II ES(engineering sample)/MP(mas...

2 20yrs

tkaku

2 20yrs tkaku

Xilinx Coregen IP Customizer Causes Exception During Customization

I'm running Xilinx ISE Webpack 7.1.04i with ISE 7.1 IP Update 3 installed on Windows XP SP2. When I run Core Generator...

3 20yrs

juendme

3 20yrs juendme

Q-bus or Unibus bus transactions in FPGA?

[Please do not mail me a copy of your followup] Has anyone implemented a Q-bus or Unibus bus interface logic in an FPGA...

12 20yrs

legalize+jeeves

12 20yrs legalize+jeeves

Bit-serial arithmetic on Spartan II

[Please do not mail me a copy of your followup] Having googled around, I see that there are a number of papers (and eve...

0 20yrs

legalize+jeeves

0 20yrs legalize+jeeves

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays