I'm trying to build a simple ALU with an adder/subtracter unit and I need both carry and overflow outputs to set the appropriate flags. However, CoreGen (6.3) doesn't let me have both carry and overflow outputs. I really don't understand why.
Xilinx designers should think twice before limiting their users in such a stupid way. Just because you don't see why someone would want both outputs, doesn't mean that somebody won't find an application that may require them. If you think that doesn't make sense, fine; that's what we have warnings for. Warn me that the value of overflow is meaningless for unsigned numbers, but don't prevent me from using it.
For instance, in this case, I don't know whether the user will add/subtract signed or unsigned numbers!!! It's up to them to decide, and then it's up to them to look into the appropriate flag. Except that I can't provide that flag using this core. Now I have to do it manually, which will most likely be less efficient. And then I'll compare it with Altera's LPM, which will of course be more efficient.
For those that don't believe that this is the case, you can see it for yourself in the following document:(Table 2)