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Xilinx V4 ISERDES problem

I am having trouble with the Xilinx ISERDES in Master/Slave configuration. I can get data from the first output register but nothing from any of the others. They are stuck low. It seems as if the data isn't clocking through although the lock and the counter on the bit clock (cam1_clk7x) scope OK.

When I go into the FPGA layout editor all the signals connections seem to be there. There is one small problem with the SHIFTIN signals of the master, in that they appear to be unconnected, and I do get a DANGLING PIN warning on these pins. These pins can not be connected to anything but another ISERDES or OSERDES so I suppose connecting them to '0' is not allowed. I tried to connect them to open as suggested by the V4 data manual but that generated an early syntax error and abort.

Any help is much appreciated. Here is the code:

-- Company: Ai Vision

-- Engineer: Brad Smallridge

-- Create Date: 17:34:16 10/24/05

-- Design Name: LVDS

-- Module Name: top - Behavioral

-- Project Name:

-- Target Device: ML40x

-- Tool versions: 7.1.4

-- Description: Accepts LVDS Channel Link / Camera Link

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity top is port( sys_rst_in : in std_logic; gpio_exp_hdr2 : in std_logic_vector( 9 downto 0); -- HDR2 diff gpio : out std_logic_vector( 3 downto 0) ); -- LEDs end top;

architecture Behavioral of top is

signal reset : std_logic; signal reset2 : std_logic; signal cam1_xclk : std_logic;

signal cam1_clk7xdiv2 : std_logic; signal cam1_lock7xdiv2 : std_logic; signal cam1_clk7x : std_logic; signal cam1_lock7x : std_logic;

signal cam1_x0 : std_logic;

signal shift1 : std_logic; signal shift2 : std_logic; signal q : std_logic_vector(6 downto 0);

signal test_counter_3 : std_logic_vector( 9 downto 0);

component dcmfx2 port( clkin_n_in : in std_logic; clkin_p_in : in std_logic; rst_in : in std_logic; clkfx_out : out std_logic; clkin_ibufgds_out : out std_logic; clk0_out : out std_logic; locked_out : out std_logic ); end component;

component dcm_140_280 port( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLK0_OUT : out std_logic; CLK2X_OUT : out std_logic; LOCKED_OUT : out std_logic ); end component;

begin

cam1_x0_ibufd_inst : IBUFDS port map ( O => cam1_x0, I => gpio_exp_hdr2(1), IB => gpio_exp_hdr2(0) );

x0_iserdes_master : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- DDR SDR DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => q(0), Q2 => q(1), Q3 => q(2), Q4 => q(3), Q5 => q(4), Q6 => q(5), SHIFTOUT1 => shift1, SHIFTOUT2 => shift2, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam1_clk7x, CLKDIV => cam1_xclk, D => cam1_x0, DLYCE => '0', DLYINC => '0', DLYRST => '0', OCLK => '0', REV => '0', SHIFTIN1 => '0', SHIFTIN2 => '0', SR => reset2 );

x0_iserdes_slave : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- "DDR" "SDR" DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => open, Q2 => open, Q3 => q(6), Q4 => open, Q5 => open, Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam1_clk7x, CLKDIV => cam1_xclk, D => '0', DLYCE => '0', DLYINC => '0', DLYRST => '0', OCLK => '0', REV => '0', SHIFTIN1 => shift1, SHIFTIN2 => shift2, SR => reset2 );

cam1_dcmfx2 : dcmfx2 port map( clkin_n_in => gpio_exp_hdr2(6), -- 40 MHz clkin_p_in => gpio_exp_hdr2(7), -- Differential pair rst_in => reset, clkfx_out => cam1_clk7xdiv2, -- 140MHz clkin_ibufgds_out => open, clk0_out => cam1_xclk, -- 40 MHz locked_out => cam1_lock7xdiv2 );

cam1_dcm_140_280: dcm_140_280 port map( CLKIN_IN => cam1_clk7xdiv2, -- 140 MHz RST_IN => reset2, CLK0_OUT => open, CLK2X_OUT => cam1_clk7x, -- 280 MHz LOCKED_OUT => cam1_lock7x );

reset

Reply to
Brad Smallridge
Loading thread data ...

one possible problem is that if the interface type is "memory", oclk need be connected.

Reply to
joseph

OK. Thanks Joe.

Well I don't really understand what the difference between OCLK and CLK are so I now have them both connected to the fast 7x clock and I am now seeing different signals on the q lines.

I also added a delay to the second DCM.

Here is the new code:

-- Company: Ai Vision

-- Engineer: Brad Smallridge

-- Create Date: 17:34:16 10/24/05

-- Design Name: LVDS

-- Module Name: top - Behavioral

-- Project Name:

-- Target Device: ML40x

-- Tool versions: 7.1.4

-- Description: Accepts LVDS Channel Link / Camera Link

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity top is port( sys_rst_in : in std_logic; -- D6 gpio_exp_hdr2 : in std_logic_vector( 9 downto 0); -- HDR2 diff gpio : out std_logic_vector( 3 downto 0) ); -- LEDs end top;

architecture Behavioral of top is

signal reset1 : std_logic; signal reset2 : std_logic; signal reset3 : std_logic; signal reset4 : std_logic;

signal cam1_xclk : std_logic; signal cam1_clk7xdiv2 : std_logic; signal cam1_lock7xdiv2 : std_logic; signal cam1_clk7x : std_logic; signal cam1_lock7x : std_logic;

signal cam1_x0 : std_logic;

signal shift1 : std_logic; signal shift2 : std_logic; signal q : std_logic_vector(6 downto 0);

signal test_counter_3 : std_logic_vector( 9 downto 0);

component dcmfx2 port( clkin_n_in : in std_logic; clkin_p_in : in std_logic; rst_in : in std_logic; clkfx_out : out std_logic; clkin_ibufgds_out : out std_logic; clk0_out : out std_logic; locked_out : out std_logic ); end component;

component dcm_140_280 port( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLK0_OUT : out std_logic; CLK2X_OUT : out std_logic; LOCKED_OUT : out std_logic ); end component;

begin

reset1 gpio_exp_hdr2(6), -- 40 MHz clkin_p_in => gpio_exp_hdr2(7), -- Differential pair rst_in => reset1, clkfx_out => cam1_clk7xdiv2, -- 140MHz clkin_ibufgds_out => open, clk0_out => cam1_xclk, -- 40 MHz locked_out => cam1_lock7xdiv2 );

reset_delay_SRL16 : SRL16 generic map ( INIT => X"0000") port map ( Q => reset2, A0 => '1', -- 16 clock delays A1 => '1', A2 => '1', A3 => '1', CLK => cam1_clk7xdiv2, D => cam1_lock7xdiv2 );

reset3 cam1_clk7xdiv2, -- 140 MHz RST_IN => reset3, -- from SRL16 CLK0_OUT => open, CLK2X_OUT => cam1_clk7x, -- 280 MHz LOCKED_OUT => cam1_lock7x );

cam1_x0_ibufd_inst : IBUFDS port map ( O => cam1_x0, I => gpio_exp_hdr2(1), IB => gpio_exp_hdr2(0) );

x0_iserdes_master : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- DDR SDR DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => q(0), Q2 => q(1), Q3 => q(2), Q4 => q(3), Q5 => q(4), Q6 => q(5), SHIFTOUT1 => shift1, SHIFTOUT2 => shift2, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam1_clk7x, CLKDIV => cam1_xclk, D => cam1_x0, DLYCE => '0', DLYINC => '0', DLYRST => '0', OCLK => cam1_clk7x, REV => '0', SHIFTIN1 => '0', SHIFTIN2 => '0', SR => reset3 );

x0_iserdes_slave : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- "DDR" "SDR" DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63 NUM_CE => 2, -- clock enables 1,2 SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => open, Q2 => open, Q3 => q(6), Q4 => open, Q5 => open, Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam1_clk7x, CLKDIV => cam1_xclk, D => '0', DLYCE => '0', DLYINC => '0', DLYRST => '0', OCLK => cam1_clk7x, REV => '0', SHIFTIN1 => shift1, SHIFTIN2 => shift2, SR => reset3 );

led_test_counter_3_process:process(cam1_clk7x) begin if( cam1_clk7x'event and cam1_clk7x='1') then if( reset3='1' ) then test_counter_3 '0'); else test_counter_3

Reply to
Brad Smallridge

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