problem with timing simulation

Hi all, i am having a problem with timing simulation. i am getting proper outputs for functional simulation and post-synthesis simulation.But after implementing the circuit on FPGA devices it is giving some kind of error message that "compnent declaration not fonud" because of this i am not able to do the timing simulation i am using activeHDL6.3 for VHDL and synplify pro for synthesis and implementation can anyone help me out in this issue


Regards Ramakrishna

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