Hello
I am trying to reverse engineer the
decimation filter core provided by xilinx core-generator.
My requirements are
- Input data rate : 8.8 M Hz 2. Decimation ratio : 2 3. Number of taps : 32 4. input and coefficeints width:16 5. symmetric filter Xilinx core generator uses
One multiplier
Two Block ram to store coefficient and input data clock frequency required : 70 MHz
How does they achieve this
I am not able to find out a structure that can expoit both decimation and symmetry of the filter to reduce the multipliers to 1 and clock frequency to 70 MHz.
I want to store the coefficient and input data in block ram so that i can save slice usage.
Can any one suggest any ideas ?
Thanks bijoy