FPGA : Decimation Filter Implementation


I am trying to reverse engineer the

decimation filter core provided by xilinx core-generator.

My requirements are

  1. Input data rate : 8.8 M Hz 2. Decimation ratio : 2 3. Number of taps : 32 4. input and coefficeints width:16 5. symmetric filter Xilinx core generator uses

One multiplier

Two Block ram to store coefficient and input data clock frequency required : 70 MHz

How does they achieve this

I am not able to find out a structure that can expoit both decimation and symmetry of the filter to reduce the multipliers to 1 and clock frequency to 70 MHz.

I want to store the coefficient and input data in block ram so that i can save slice usage.

Can any one suggest any ideas ?

Thanks bijoy

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For starters.. you shouldn't mention "reverse-engineer" and "Xilinx core generator" in here.. this is a monitored group by both Altera and Xilinx... both will not appreciate it. (not to mention those of us who make our living from the IP business)


32 4. input and coefficeints width:16 5. symmetric filter Xilinx core generator uses

: 70 MHz

symmetry of the filter to reduce the multipliers to 1 and clock frequency to

70 MHz.

save slice usage.

Reply to
Simon Peacock

Hi Simon, He could well have a legitimate reason for reverse-engineering the core. Perhaps he wants to see if anyone is infringing his own patent? Although, from his post, I guess not. Also, I believe it's lawful to reverse-engineer something which is protected by trade secrets rather than a patent. That is, unless you stole the thing you're reverse-engineering. Still, as you say, best not to advertise it whatever the reasons. Cheers, Syms.

p...s... I think there's something wrong with your full stop key... In a lot of your posts it keeps coming out in duplicate or triplicate... ;;;---)))

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'...' is a pause as opposed to '.' a stop. Even text to speech recognises this. I will try to refrain... maybe

But reverse engineering can be done to anything. A copyright message is all you need to 'stop' it but that isn't usually enough. I myself have been designing for 20+ years and have purposefully released things as GPL so they can be public. Other stuff (hardware and software) is most defiantly not public. I have some rather flash UARTS, Ethernet Interfaces and E1 units. These add value to both my pay-packet each month and to my companies standing. They also make sure that each company review, there is a reason to keep me employed. I've also started studying towards a BE-Tech and possibly a Masters. So why do I think its not OK to copy? There are multiple reasons above.

The only time I would recommend breaking a copyright is when the company is defunct and you need to do an update but even then someone might have walked away with the copyright/patent.





Reply to
Simon Peacock

Yeah, sorry, I was just being a smartass. There's an interesting Wikipedia article all about the ellipsis.

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OK, but if 'reverse engineering' is just finding out how something works, then that's fine, yes? For example, books are copyrighted, but you can still read them. As to what you then do with the knowledge you gain, I guess that's where the line between good and evil is. If you read a copyrighted electronics text book, it's ok to use the knowledge you gain to design electronics, or even to write your own textbook, provided you don't copy verbatim. If you reverse engineer a FIR filter, it's ok (legally and morally?) to use the knowledge you've gained to create your own, provided it's not a direct copy. Maybe! In the US, maybe the DMCA has some ramifications as to the legality of reverse engineering. Interesting subject, I guess there's not a black and white answer. Cheers, Syms.

Reply to

Yews and no.. it could be argued that books are by design, designed to be read. Take a look at the copyright message for most software. "cannot be disassembled for any purpose" is a very common phrase

"In order to protect them you may not decompile, reverse engineer, disassemble, or otherwise reduce the Software to a human-perceivable form."

This is from the Xilinx EULA for the development tools. I don't have core-generator handy, but as you can see, they don't want you to view in any shape or form their software. Altera might be different but that is because their tools were built with or include GNU

You can of course copy directly from a book, I think anyone would be hard pressed to stop someone or even to prove they had exclusive rights to something found in print, you would only have to find it in a different book printed before the one in question to automatically invalidate any clams.

Of course, the invention of time travel will make all patents null and void :-)







Reply to
Simon Peacock

Including the patent on the time travel machine?!! Cheers, Syms.

Reply to

That sort of phrase is common in EULAs, not copyright messages. And in most countries, it is legally unenforceable (IANAL, of course). In fact, you'd have a great deal of trouble finding a software EULA that is entirely legally enforceable in any jurisdiction. Reverse engineering is a perfectly legal technique for certain purposes (interoperability with other software is a prime example - look at samba), and disassembly, etc., is part of that. Of course, directly copying an existing system is generally illegal, whether by reverse engineering or otherwise.

Reply to
David Brown

Hi all I don't mean reverse engineering... in actual sense.

I need a Decimation filter structure where i can update my coefficients(ie access is provided to the user to update filter coefficient, which is not provided in xilinx core generated module). I have a structure of FIR filter built by me, but that uses more resources than provided by xilinx core generator.

As all of us know the decimation structure there is nothing great in that.

But how to use xilinx block ram to exploit the symmetry of the coefficient may not be known to all. I am looking for a filter structure not VHDL/Verilog code.

I will be very glad to use xilinx provided cores if it suits my requirement of coefficient updation, unfortunately they are not supporting it.

regards bijoy

Reply to

hey bijoy

i am trying to implement a DDC with the xilinx virtex II-pro XUPV2P board. since you have started on an FPGA project, and are in the process of optimizing, i was wondering if you could help me in figuring out how to interface LVDS/CMOS i/o - data to be demodulated - with system generator or edk. i greatly appreciate your help.


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