Latest threads in Field-Programmable Gate Arrays

ISE project with a Microblaze submodule: timing constrains warning

I have an ISE project where I have a Microblaze submodule, containing 2 CPUs. When I try to make timing constrains a wa...

1 20yrs

raybakk

1 20yrs raybakk

help: how to use ICAP of Virtex-II ?

i want to get an demo design reference of ICAP. if anyone want to give me a hand, many thanks here. ^_^ my e-mail is sni...

1 20yrs

lioupayphone

1 20yrs lioupayphone

software application on the virtex-ii pro

Hi All, I have Linux up running for PPC on the virtex-ii pro board (XUPV2P). I'm new to embedded system design. Anyhow,...

2 20yrs

dasani8888

2 20yrs dasani8888

Patents and (possible) Plagiarism, Anyone ever been in a similar situation?

Ah, this is interesting. Weng and I have been having this extended chat on median filters (hope it did not bore anyone)...

27 20yrs

john.l.smith

27 20yrs john.l.smith

More beginner's verilog questions

After I found out that I couldn't syntesize a lot of the verilog code ( http://awlnk.com/?aRts ), I had to redesign how...

45 20yrs

google

45 20yrs google

Mixing XC9500 and XC9500XL, also small qty suppliers

Hi, I've just finished tweaking all the Verilog code for my Atari DVG reimplementation. Problem is, I've hit the macroc...

7 20yrs

philpem

7 20yrs philpem

Virtex-4 Startup

Hi all! Can some one be kind and explain me the startup cycle of an Virtex-4? Is the logic activated AFTER the GSR is a...

3 20yrs

taileb.mehdi

3 20yrs taileb.mehdi

Virtex II Pro XC2VP100

Hi friends The Virtex II pro (XC2VP100) device is not Configuring through Impact7.1 When i try to check with CRO what i...

6 20yrs

murugs_india

6 20yrs murugs_india

Differential Pin Pairs in Lattice EC FPGAs

Hi newsgroup, Altera has a command which is described as follows: >The Show Differential Pin Pairs command shows a red...

4 20yrs

ALuPin

4 20yrs ALuPin

Problem with downloading elf file to ML403 using XMD

Hi, I am currently working on a new board based on a Xilinx Virtex-4 FPGA.We are using a ML403 board as SW a developmen...

1 20yrs

easy.anderson

1 20yrs easy.anderson

where can i get a release copy of ISE 8i?

many thanks! ^_^

2 20yrs

lioupayphone

2 20yrs lioupayphone

Powering unused MGTs in XC4VFX20CES2

Hi! I just read the Virtex 4 documentation and the errata sheet for the XC4VFX20CES2 device and I'm thinking about one...

4 20yrs

usenet

4 20yrs usenet

How to use ISE FPGA Editor to compare timing path easily?

Hi, I have a memory controller desing implemented for Virtex4 chip. I know there are some timing problem and suspect th...

1 20yrs

linq936

1 20yrs linq936

rs232 and picoblaze :)

Hi all ! I bought a S3board from digilent. I ran some program to test it, included a serial parallel multiplier :) I'm...

2 20yrs

xavier.tastet

2 20yrs xavier.tastet

Altera based Video development board

Hi, I am looking for a FPGA based video prototype board with the following components: 1 Video decoder for 1 color comp...

5 20yrs

markus.knauss

5 20yrs markus.knauss

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