Latest threads in Field-Programmable Gate Arrays

know the Xilinx line? I need a good FAE or TSE in Austin, Texas

For a major kickass distributor. ASAP interview. Anyone ready for leveraging their career financially? snipped-for-priva...

0 20yrs

brett

0 20yrs brett

Looking for QuickLogic DeskFab programmer, new or used

Please email offers. Looking to purchase immediately.

0 20yrs

turbo.satan

0 20yrs turbo.satan

FPGA Implementation Of Real Time Data Compression

I Am Doing A Project On FPGA Using LZ Algo In VHDL. Can SomeOne Help On how to go about it and with code also i will be...

0 20yrs

apurvewarrior

0 20yrs apurvewarrior

How to simulate Virtex-4 PPC, MAC, etc. ?

Hello! Having finished a board design with a Virtex-4FX and with promising leads on the silicon, I sat down to begin my...

1 20yrs

acetylcholinerd

1 20yrs acetylcholinerd

verification tools?

hello group! (and sorry for the cross-posting) I am working on a complex FPGA prototype and have already a feeling that...

1 20yrs

burn.sir

1 20yrs burn.sir

Get Start for XtremeDSP Developement Board -IV

Dear Sir, There have a Xilinx/Nallatech Virtex4 development board beside me, on which there has 2 ch ADC (105MSPS), 2ch...

1 20yrs

chengwelsion

1 20yrs chengwelsion

ISE 8.1i on Fedora Core 4 (64-bit)

In general, ISE 8.1i seems to install and work just fine on my Athlon 64 system running Fedora Core 4 (64-bit). ISE Sim...

3 20yrs

eric

3 20yrs eric

Interfacing externally clocked data to an FPGA (Spartan 3)

Hi, First time poster here. I'm using Xilinx's cheap Spartan 3 Starter Kit Board to create a simple VGA "controller" (f...

6 20yrs

bart_trzynadlowski

6 20yrs bart_trzynadlowski

Avnet hav2 s3e starter kit?

According to The spartan 3e starter kits are available yet xilinx says they are not ? Alex

17 20yrs

alxx.nospam

17 20yrs alxx.nospam

Inverter Chain Synthesis Problem

Hi, I work on Xilinx ISE, and my synthesis tool is XST and synplify. I use verilog to write a Inverter Chain (delay ) l...

10 20yrs

zhushenli

10 20yrs zhushenli

Scrambled Net Names!

I am implementing a design in a Xilinx FPGA, using ISE 6.1.3i and for reasons that are not important right now, have to...

1 20yrs

simon.stockton

1 20yrs simon.stockton

Xilinx DCM Shuts down at 75degree centigrade

Hi, I am using a Xilinx Virtex Pro P20 FPGA.The system clock (155M) is comes out of a DCM FX which is phase locked to i...

5 20yrs

debashish.hota

5 20yrs debashish.hota

Parallel Cable III is not detected

Hi, Xilinx iMPACT is not detecting my parallel cable III when I am trying to download projects to the board. My board i...

6 20yrs

singhal.prateek

6 20yrs singhal.prateek

Digilent SRAM Controller

Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is desi...

6 20yrs

alastairlynch

6 20yrs alastairlynch

How to simulate a .NMC macro?

A hard macro created with fpga editor is saved in a .nmc file. It can be saved in a .ncd design file. I first thought o...

3 20yrs

john.wo54

3 20yrs john.wo54

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