Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

FPGA Implementation Of Real Time Data Compression

I Am Doing A Project On FPGA Using LZ Algo In VHDL. Can SomeOne Help On how to go about it and with code also i will be...
0 comments posted 20yrs
posted by apurvewarrior
0 comments posted 20yrs posted by apurvewarrior

How to simulate Virtex-4 PPC, MAC, etc. ?

Hello! Having finished a board design with a Virtex-4FX and with promising leads on the silicon, I sat down to begin my...
1 comments posted 20yrs
posted by acetylcholinerd
1 comments posted 20yrs posted by acetylcholinerd

verification tools?

hello group! (and sorry for the cross-posting) I am working on a complex FPGA prototype and have already a feeling that...
1 comments posted 20yrs
posted by burn.sir
1 comments posted 20yrs posted by burn.sir

Get Start for XtremeDSP Developement Board -IV

Dear Sir, There have a Xilinx/Nallatech Virtex4 development board beside me, on which there has 2 ch ADC (105MSPS), 2ch...
1 comments posted 20yrs
posted by chengwelsion
1 comments posted 20yrs posted by chengwelsion

ISE 8.1i on Fedora Core 4 (64-bit)

In general, ISE 8.1i seems to install and work just fine on my Athlon 64 system running Fedora Core 4 (64-bit). ISE Sim...
3 comments posted 20yrs
posted by eric
3 comments posted 20yrs posted by eric

Avnet hav2 s3e starter kit?

According to The spartan 3e starter kits are available yet xilinx says they are not ? Alex
17 comments posted 20yrs
posted by alxx.nospam
17 comments posted 20yrs posted by alxx.nospam

Inverter Chain Synthesis Problem

Hi, I work on Xilinx ISE, and my synthesis tool is XST and synplify. I use verilog to write a Inverter Chain (delay ) l...
10 comments posted 20yrs
posted by zhushenli
10 comments posted 20yrs posted by zhushenli

Scrambled Net Names!

I am implementing a design in a Xilinx FPGA, using ISE 6.1.3i and for reasons that are not important right now, have to...
1 comments posted 20yrs
posted by simon.stockton
1 comments posted 20yrs posted by simon.stockton

Xilinx DCM Shuts down at 75degree centigrade

Hi, I am using a Xilinx Virtex Pro P20 FPGA.The system clock (155M) is comes out of a DCM FX which is phase locked to i...
5 comments posted 20yrs
posted by debashish.hota
5 comments posted 20yrs posted by debashish.hota

Parallel Cable III is not detected

Hi, Xilinx iMPACT is not detecting my parallel cable III when I am trying to download projects to the board. My board i...
6 comments posted 20yrs
posted by singhal.prateek
6 comments posted 20yrs posted by singhal.prateek

Digilent SRAM Controller

Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is desi...
6 comments posted 20yrs
posted by alastairlynch
6 comments posted 20yrs posted by alastairlynch

How to simulate a .NMC macro?

A hard macro created with fpga editor is saved in a .nmc file. It can be saved in a .ncd design file. I first thought o...
3 comments posted 20yrs
posted by john.wo54
3 comments posted 20yrs posted by john.wo54

D FLIP -FLOP

hiii i need immeadite help... i have to deliver a presentation. suppose i have to verify a D flip flop, what are the ve...
2 comments posted 20yrs
posted by abrar_ahmed_313
2 comments posted 20yrs posted by abrar_ahmed_313