Hi all! Can some one be kind and explain me the startup cycle of an Virtex-4? Is the logic activated AFTER the GSR is asserted of should I add some logic to wai for the end of the startup? For what is the SARTUP_VIRTEX4 primitive?
Cheers Mehdi
Hi all! Can some one be kind and explain me the startup cycle of an Virtex-4? Is the logic activated AFTER the GSR is asserted of should I add some logic to wai for the end of the startup? For what is the SARTUP_VIRTEX4 primitive?
Cheers Mehdi
See XAPP719 for one possible use of the STARTUP_VIRTEX4 primitive (in this case in combination with the USR_ACCESS_VIRTEX4 primitive).
- Peter
GaLaKtIkUs? wrote:
Hi Mehdi, GSR will reset all of the internal flipflops to a known state (usually 0 - unless otherwise specified by the bitstream). There are however other chip events that happen after GSR.
The best marker for the end of the FPGA startup is the EOS signal which is an output available from the STARTUP_VIRTEX4 primitive. EOS stands for "end of startup".
- Vic
GaLaKtIkUs? wrote:
Hi again! When instantiating the STARTUP_VIRTEX4 shoul I connect all the inputs? Is it possible to leave them all (inputs) unconnected? from where should the input GSR come from ?
Thnaks a lot for interest and help Mehdi
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