How to use ISE FPGA Editor to compare timing path easily?

Hi, I have a memory controller desing implemented for Virtex4 chip. I know there are some timing problem and suspect that it is because the delay difference between the different timing pathes are too much.

There is a common clock generated from DCM driving all the logic.

Currently I launtch the desing in FPGA Editor and try to collect the delay for all the pathes, but that is really a lot of work. I start from the DCM output, count the delay one net by one net up to the pad, and sum them up.

And do this for all the pathes seem impossible.

I wonder if there are any trick to do this kind of thing faster?

Thanks.