Field-Programmable Gate Arrays

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Can somone work on the pci express project?

I wanna to write a pci express endpoint ,and I don't have a idea that if this is too difficult,But the ipcore from the f...
6 comments posted 20yrs
posted by bjzhangwn
6 comments posted 20yrs posted by bjzhangwn

FREE Spartan 3e Sample Pack

There is no free lunch but there is FREE Spartan3E board this Christmas! As it doesnt look that an announcement from Xi...
0 comments posted 20yrs
posted by antti
0 comments posted 20yrs posted by antti

Image processing libraries and VHDL

Hello, I am starting to work on Spartran FPGA. and most of my work will be related to image processing. I never worked...
1 comments posted 20yrs
posted by conphiloso
1 comments posted 20yrs posted by conphiloso

Virtex-4FX and ethernet mac

Hallo, I'm planning to buy a development board based on Virtex-4FX. I have read about V-4FX that ethernet mac is inside...
5 comments posted 20yrs
posted by marcotoschi
5 comments posted 20yrs posted by marcotoschi

SystemACE problem

Hi, As a student I'm working on a project which requires us to read a file from a Compact Flash card using the Xilinx S...
3 comments posted 20yrs
posted by arne.demmers
3 comments posted 20yrs posted by arne.demmers

Spartan3e and ChipScope

Hi I am having extreme trouble with ChipScope and Spartan3e (using the Spartan3E Sample Pack PCB from digilent). ISE 7....
13 comments posted 20yrs
posted by antti
13 comments posted 20yrs posted by antti

microblaze & nios

Which one should I choose? from the aspects below:performance,money ,resourse What i can use and so on.thanks!
0 comments posted 20yrs
posted by bjzhangwn
0 comments posted 20yrs posted by bjzhangwn

RTL for Z8000 series CPU?

Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam...
41 comments posted 20yrs
posted by ajcrm125
41 comments posted 20yrs posted by ajcrm125

edif to vhd black box

Hi all, My simple question, is there any tools to auto-generate a vhdl instantiate template from the netlist file? I fo...
1 comments posted 20yrs
posted by ccon67
1 comments posted 20yrs posted by ccon67

Synplicity and the EDK

I am evaluating Synplicity and am trying to run a comparison on the system that we have developed in the EDK. Basically...
1 comments posted 20yrs
posted by mottoblatto
1 comments posted 20yrs posted by mottoblatto

Going insane - Xilinx VGA controller...

Dear Group, I am designing an LCD controller, straight VGA using a 6.5" TFT (60Hz and a 25MHz dot clock) with a 32MBit...
13 comments posted 20yrs
posted by peter.halford
13 comments posted 20yrs posted by peter.halford

Cordic v2.0 : cordic translate algorithm problem

I treid to use the tanslate mode of cordic. Unfortunately I always get a wrong phase_out result in the simulation. Is it...
0 comments posted 20yrs
posted by tobiaskoeber
0 comments posted 20yrs posted by tobiaskoeber

Opencores Can Controller

Hallo, I would to try this core. Where I could find the documentation for 8051 interface? Has anyone ever used it? Many...
2 comments posted 20yrs
posted by marcotoschi
2 comments posted 20yrs posted by marcotoschi

Xilinbx Online store XC2C32A, XC2C64A missing ?

Anyone know why these two smaller CPLDs seem to have vanished from the Xilinx Webstore ? Other parts show 'out of stock...
2 comments posted 20yrs
posted by no.spam
2 comments posted 20yrs posted by no.spam