Field-Programmable Gate Arrays

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Xilinbx Online store XC2C32A, XC2C64A missing ?

Anyone know why these two smaller CPLDs seem to have vanished from the Xilinx Webstore ? Other parts show 'out of stock...
2 comments posted 20yrs
posted by no.spam
2 comments posted 20yrs posted by no.spam

lpc922

Hello Everyone iam new this grp sole reason to join this group is that i am finding myself unable to find a suitable al...
3 comments posted 20yrs
posted by anshat
3 comments posted 20yrs posted by anshat

Buffers/Line drivers for 6pin JTAG?

Hello, everyone! I am trying to adapt Spartan 3 Starter Kit board as a standalone board for one of my projects. To down...
2 comments posted 20yrs
posted by interpasha
2 comments posted 20yrs posted by interpasha

Spartan 3 Digilent Board Expansion Connectors

I am working on a project that is taking a clock and inerfacing it with PLL to get a set of variable clock divisions. I...
1 comments posted 20yrs
posted by jks2999
1 comments posted 20yrs posted by jks2999

8 in clock mux

Below is the code I use to mux 8 asynchronous clocks on a Spartan3. I guess this method is safer than using LUT muxes a...
0 comments posted 20yrs
posted by mleikvol
0 comments posted 20yrs posted by mleikvol

HOW IS GREY BOX VERIFICATION DONE

hiii friends... can any one tell me or explain to how is grey box verification done??? black box and white box is clear...
0 comments posted 20yrs
posted by abrar_ahmed_313
0 comments posted 20yrs posted by abrar_ahmed_313

Interactive Logic

Hello everyone. If you are interested in new ways to develop FPGA based logic, where signals and data can be viewed and...
0 comments posted 20yrs
posted by andy.ward
0 comments posted 20yrs posted by andy.ward

Xilinix Modular Flow

Hi all, My question to u all is about the Xilinix Modular design.......any working on dynamically reconfigurable FPGAs?...
3 comments posted 20yrs
posted by gennie_81
3 comments posted 20yrs posted by gennie_81

Place and Route Algorithms

Hello everyone. Does anyone know where I can find information about the place and route algorithms used for FPGAs, and...
26 comments posted 20yrs
posted by marcoa.castellon
26 comments posted 20yrs posted by marcoa.castellon

Virtex-4 clocking

Hi fellow engineers, I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some experience in board desi...
5 comments posted 20yrs
posted by quinn_the_esquimo
5 comments posted 20yrs posted by quinn_the_esquimo