Latest threads in Field-Programmable Gate Arrays

call for paper,expresscard specification

Can anyone who have it share it?

0 20yrs

bjzhangwn

0 20yrs bjzhangwn

lpc922

Hello Everyone iam new this grp sole reason to join this group is that i am finding myself unable to find a suitable al...

3 20yrs

anshat

3 20yrs anshat

Buffers/Line drivers for 6pin JTAG?

Hello, everyone! I am trying to adapt Spartan 3 Starter Kit board as a standalone board for one of my projects. To down...

2 20yrs

interpasha

2 20yrs interpasha

Spartan 3 Digilent Board Expansion Connectors

I am working on a project that is taking a clock and inerfacing it with PLL to get a set of variable clock divisions. I...

1 20yrs

jks2999

1 20yrs jks2999

8 in clock mux

Below is the code I use to mux 8 asynchronous clocks on a Spartan3. I guess this method is safer than using LUT muxes a...

0 20yrs

mleikvol

0 20yrs mleikvol

Can anyone have the evaluation board from xilinx and altera?

I am interest in the embeded system in the fpga,but I have no money to buy the board from xilinx or altera,Anyone who ha...

1 20yrs

bjzhangwn

1 20yrs bjzhangwn

FPGA DDR controller - CKE signal... do I need a pull down?

Hi guys, I've written a DDR controller, runs on a virtex2 and interfaces a sodimm 256MB. I've got a problem initialisat...

1 20yrs

delete

1 20yrs delete

Is there anyboay work on the subject with the embeded system in the fpga?

Now I want to implement a arm core in the xilinx v4 or v2,but I can't get the soft ip core,anybody konw how to get the...

0 20yrs

bjzhangwn

0 20yrs bjzhangwn

HOW IS GREY BOX VERIFICATION DONE

hiii friends... can any one tell me or explain to how is grey box verification done??? black box and white box is clear...

0 20yrs

abrar_ahmed_313

0 20yrs abrar_ahmed_313

exception (0xe06d7363) when creating a MicroBlaze from the ISE environment

When I create an embedded processor from the ISE environment an exeption popps up whenever I close the XPS. The exeptio...

0 20yrs

raybakk

0 20yrs raybakk

Interactive Logic

Hello everyone. If you are interested in new ways to develop FPGA based logic, where signals and data can be viewed and...

0 20yrs

andy.ward

0 20yrs andy.ward

Xilinix Modular Flow

Hi all, My question to u all is about the Xilinix Modular design.......any working on dynamically reconfigurable FPGAs?...

3 20yrs

gennie_81

3 20yrs gennie_81

Place and Route Algorithms

Hello everyone. Does anyone know where I can find information about the place and route algorithms used for FPGAs, and...

26 20yrs

marcoa.castellon

26 20yrs marcoa.castellon

Virtex-4 clocking

Hi fellow engineers, I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some experience in board desi...

5 20yrs

quinn_the_esquimo

5 20yrs quinn_the_esquimo

ISE project with a Microblaze submodule: timing constrains warning

I have an ISE project where I have a Microblaze submodule, containing 2 CPUs. When I try to make timing constrains a wa...

1 20yrs

raybakk

1 20yrs raybakk

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