I have used other VHDL simulators, but I am now trying to run the Xilinx ISE simulator in Foundation 7.1 for the first time. As you can see below, I'm not having much success.
I get the following message:
Compiling vhdl file "Match8.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Parsing "match8_lau.prj": 0.73 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen UNISIM/VPKG: 0.13 Codegen UNISIM/VPKG: 0.09 Codegen UNISIM/VPKG: 0.09 Codegen UNISIM/VPKG: 0.11 Codegen UNISIM/VPKG: 0.11 Codegen unisim/VPKG: 0.11 Codegen unisim/VPKG: 0.09 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen UNISIM/VCOMPONENTS: 0.03 Codegen UNISIM/VCOMPONENTS: 0.00 Codegen unisim/SRLC16E: 0.00 Codegen unisim/SRLC16E: 0.02 Codegen unisim/SRLC16E: 0.00 Codegen unisim/MUXCY: 0.00 Codegen unisim/MUXCY: 0.01 Codegen work/MATCH8: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen unisim/SRLC16E/SRLC16E_V: 0.02 Codegen unisim/SRLC16E/SRLC16E_V: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen unisim/MUXCY/MUXCY_V: 0.00 Codegen unisim/MUXCY/MUXCY_V: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen work/MATCH8/BEHAVIOR: 0.01 ERROR: Fuse failed
When trying to simulate a simple 8 bit identity comparator that is known to work fine. Basically no matter what code I try to simulate, I get the ERROR: Simulator:222 error.
It looks that something very basic is wrong, like some environment setting, but I have found no information on this error anywhere. The code compiles into a bitstream without any problems, and the VHDL syntax checker works fine, it just doesn't want to simulate.
Any suggestions would be greatly appreciated.
Thanks
Chris Johnson