Field-Programmable Gate Arrays

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Help! FIR Filter - MATLAB fdatool - VHDL

Hi, I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that...
3 comments posted 20yrs
posted by emeltasyurek
3 comments posted 20yrs posted by emeltasyurek

dma on fpga pci card

I had posted earlier my issues with Fpga card. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534...
7 comments posted 20yrs
posted by nitesh.guinde
7 comments posted 20yrs posted by nitesh.guinde

DMA using fpga pci card

I had posted earlier my issues with Fpga card. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534...
0 comments posted 20yrs
posted by nitesh.guinde
0 comments posted 20yrs posted by nitesh.guinde

DMA with powerspan II -Fpga card

I had posted earlier my issues with Fpga card. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534...
4 comments posted 20yrs
posted by nitesh.guinde
4 comments posted 20yrs posted by nitesh.guinde

DMA over pci

I had posted a few weeks back about my issue http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/7353463...
0 comments posted 20yrs
posted by nitesh.guinde
0 comments posted 20yrs posted by nitesh.guinde

ISE 7.1 & ModelSim - Simulating Internal Signals

Hi All, I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and routing behavior in a Virtex II part....
8 comments posted 20yrs
posted by billingworth
8 comments posted 20yrs posted by billingworth

CRC error correction

I am looking at using a CRC to provide single bit error correction and multiple bit error detection. I have worked with...
16 comments posted 20yrs
posted by spamgoeshere4
16 comments posted 20yrs posted by spamgoeshere4

Programming Xilinx PowerPC

Hello, I have a Veritex-4 PCI board and I like to program the PowerPC on it. I don't have the EDK from Xilinx. Here are...
11 comments posted 20yrs
posted by ma
11 comments posted 20yrs posted by ma

Chipscope Pro

I'm confused (doesn't take much these days). I'm thinking of using Chipscope. The Xilinx shop says 'License Note: In or...
3 comments posted 20yrs
posted by dave.garnett
3 comments posted 20yrs posted by dave.garnett

FPGA -> ASIC`

Hello: I have absolutely no experience in ASIC design. I do however have experience in FPGA. I have a CPU design that i...
4 comments posted 20yrs
posted by emh203
4 comments posted 20yrs posted by emh203

Asynch. signal

Hello, I have interfaced a 8 bit parallel data bus and a clock signal of the USB device to a CPLD. I need to store 32bi...
8 comments posted 20yrs
posted by conphiloso
8 comments posted 20yrs posted by conphiloso

Spartan3 DFS jitter reduction

Xapp462 (bottom page 59) says "The DFS clock outputs, CLKFX and CLKFX180, remove some amount of incoming clock jitter......
0 comments posted 20yrs
posted by mleikvol
0 comments posted 20yrs posted by mleikvol

Ethernet Encoding scheme

Hi All, I want some guidence for encoding schemes used in ethernet I know that for gigabit ethernet mostly the 8b10b en...
6 comments posted 20yrs
posted by kedarpapte
6 comments posted 20yrs posted by kedarpapte