Field-Programmable Gate Arrays

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NGDBuild Error 604

I have been playing around with a script provided by Synplicity to synthesize EDK projects using synplify. It basically...
0 comments posted 20yrs
posted by mottoblatto
0 comments posted 20yrs posted by mottoblatto

Virtex-4 FX12 EMAC with ISE WebPack

First, thank you xilinx for moving the functionality previously available in Base-X to the free WebPack. I was somewhat...
3 comments posted 20yrs
posted by acetylcholinerd
3 comments posted 20yrs posted by acetylcholinerd

Signal Skew

I need to know the expected signal skew inside the XC2VP30 (FF1152 package) for the various types of routing resources....
1 comments posted 20yrs
posted by billingworth
1 comments posted 20yrs posted by billingworth

XC3S100/250/500E Availability?

Hello all, Trying to track down availability of some XC3S500E parts (or 100/250 3E's) in PQ208 package. I've tried Avne...
1 comments posted 20yrs
posted by jceven
1 comments posted 20yrs posted by jceven

Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

So I need some help getting started with programmable logic and VHDL. In the past all I have done in the programmable l...
29 comments posted 20yrs
posted by cdsmith69
29 comments posted 20yrs posted by cdsmith69

Clock related questions

Using the internal 50 MHz clock of the Spartan 3 board, my design synthesized to a speed of 200MHz . If I want my desig...
1 comments posted 20yrs
posted by ramya.sriragh
1 comments posted 20yrs posted by ramya.sriragh

Virtex2 I/O state in configure phase

Hi It makes me weird. Till now I thought that on all I/O's is highZ while V2 is configured. But it just before starting...
9 comments posted 20yrs
posted by jerzy.gbur
9 comments posted 20yrs posted by jerzy.gbur

Do you name your FPGA?

I've known lots of ASIC designers that name their device something cool like vader or dilbert. Do people name their FPG...
11 comments posted 20yrs
posted by fourbeans
11 comments posted 20yrs posted by fourbeans

Synplify Pro batch mode

Hey all, I am trying to run a script that Synplicity has provided to integrate synplify pro with the EDK. I think it is...
2 comments posted 20yrs
posted by mottoblatto
2 comments posted 20yrs posted by mottoblatto

EDK 8.1i

Hallo, does anyone knows when will be available? And multi-port memory controller will be included? Many Thanks Marco
2 comments posted 20yrs
posted by marcotoschi
2 comments posted 20yrs posted by marcotoschi

Xilinx DCM

Hi all, i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which you need to provide a feedback clock fo...
4 comments posted 20yrs
posted by debashish.hota
4 comments posted 20yrs posted by debashish.hota

What kind of cpu is suit for me?

Now I want to design a RISC cpu for study the cpu architecture, and I am puzzled about how to start? Whether should I s...
5 comments posted 20yrs
posted by hitsx
5 comments posted 20yrs posted by hitsx

Timing constraints (again)

Hi all, What should I read to find out about timing constraints in detail? not just syntax but some theory. and how are...
2 comments posted 20yrs
posted by subhasri.krishnan
2 comments posted 20yrs posted by subhasri.krishnan

Costas Loop Carrier Recovery

Hi, I'm trying to implement a second order costas loop for carrier recovery in AM DSB-SC and BPSK. I 've done simulatio...
0 comments posted 20yrs
posted by x_emrah_x
0 comments posted 20yrs posted by x_emrah_x