How to keep the design from Synplify or XST optimizing

hi, as far as i know this is because u r not using those RAMs (the synthesize tools will optimize those are not using in your design). to remove such optimisation u can untick the options in the synthesize(properties) like register duplication and equvalent register removal.

Search the keyword "keep" or "preserve" in the tool manuals and go from there.

HTH, Jim

One silly idea: check your address register to make sure it's defined as a

thank u for ur tips,the synthesis command "syn_keep" "syn_noprune" and "syn_preserve" can prevent instances or reg or wire from optimizing. Now I hope to keep the net connections and stop optimizing the whole design, fit the design to a FPGA, is there any solution?

You can also use syn_hier ="hard" for Xilinx in synplicity to force it to respect the component boundaries so that it doesn't share stuff between hierarchical components.