Help! FIR Filter - MATLAB fdatool - VHDL


I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector):

IF reset = '1' THEN delay_pipeline(0 TO 7) (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0)

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understand it correctly.

In that case, I would get a vhdl simulator and test the code.

-- Mike Treseler

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Mike Treseler

Emel schrieb:

Hi Emel, for instant relief follow Mikes advice and get yourself a simulator, you may need it anyway sometime.

But to help you understand you should learn the difference between variables and signals in VHDL. Signals (assigned with

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From: "" Newsgroups: comp.arch.fpga Subject: Re: Help! FIR Filter - MATLAB fdatool - VHDL Date: Mon, 09 Jan 2006 05:04:35 -0800

Hi Emel,

You could instead use Synplify DSP

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to generate either HDL or Verilog code for a filter design from a filter specification given to the fdatool in Matlab. The software is integrated into Matlab and allows you to develop more complex systems (which your filter could be a part of) for implementation on an FPGA using the block-based Simulink environment, and can generate code that is optimized for different FPGAs from both Altera and Xilinx.

Best wishes, Jonathan

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