I am starting a new design and would like to connect the Virtex-4 PowerPC to another external device with a PCI bus. The IP cores I find on the Xilinx web site seem to suggest a connection from the PLB to the OPB though a bridge, and then another bridge from the OPB to the PCI bus.
Is this not a major performance bottleneck? Why not connect the PCI to the PLB directly? In the IBM/AMCC processors that I have worked with, the 405GP and 440GX, the PCI (and PCI-X) bridges are connected to the PLB, not the OPB. The OPB in these designs is used only for low speed peripherals.
I am about to negotiate an agreement with Xilinx to purchase of a number of IP cores, but I am not clear on all that I would need to implement a complete PCI solution. Can anyone advise?
The device I am attaching the Virtex-4 to is an AMCC PPC440GX with a PCI / PCI-X interface. No other devices on this bus. I am still not sure if I want to make it a 32 or 64 bit connection, extra bandwidth is good but the extra pin requirements and PCB routing challenges are bad.
Realistically, what kind of performance can I expect?
Is it at all realistic to except the external device to be able to receive full rate data from 2 GMACs inside the Xilinx? What about data transfer speed (block copy) from the external device to a 64 bit DDR memory controller on the PLB?
Tom.