ISE 7.1 & ModelSim - Simulating Internal Signals

As I know ,in verilog,if the signals you specifys is not in use,and the synthesis tool(synplify pro etc)will optimize it,and will give a warning and remove it.

In Modelsim, once the design has been loaded, using the GUI interface, you can open windows displaying the design structure (as a directory type tree), and the named signals. Navigate to the design sub-unit you need to monitor; its signals are listed in the "signals" window. Select those you need, right click, and "add selected signals to Wave window".

Now simulate and they will be displayed.

If you missed some, add them, restart, and simulate again.

You can also do the same via TCL script of course; the GUI approach simply generates the relevant script commands. Or you can save the Wave window format as a ".do" script to recreate this test later.

Caveat: above refers to ModelSim SE; I believe it's true of XE but I'm not 100% certain)

- Brian

Hi,

Sure, it also applies for MXE.

Yes, you should be able to click on UUT (unit under test) and get access to internal logic. Look for the Workspace window and click on the 'sim' tab. You should see UUT listed in the directory tree.

Thanks for the advice, however there is still have one issue. After the internal signal is added to the waveform and the simulation is restarted (by reissuing the .do command) the simulation restarts, but the newly add signal is removed from the waveform. What am I missing?

-Brendan

ModelSim.

signals

"add

the

right

A cut and past of the ADD WAVE command from the modelsim command line to the .do file.

-- Mike Treseler

Or a save of the (modified) wave.do file ( = "save" in the wave window)

- Brian

Thanks All. Much appreciated.

-Brian

the

restarted (by

signal