Field-Programmable Gate Arrays

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Virtual Pin in Xilinx ISE

Greetings, I've used the Altera/Quartus II tool set for a previous project, and my next project will likely use the Xil...
5 comments posted 20yrs
posted by jeremy.lees
5 comments posted 20yrs posted by jeremy.lees

Creating Multiple Configuration PROM File

Hello. Can anyone direct me to a piece of Xilinx literature that explains how to load more than 1 config file into progr...
18 comments posted 20yrs
posted by robnstef
18 comments posted 20yrs posted by robnstef

Modelsim problem

Hello, I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. However, if I use the "add wave *" command,...
5 comments posted 20yrs
posted by jaime.aranguren
5 comments posted 20yrs posted by jaime.aranguren

need for a group FAQ?

Hello everyone While I was browsing the newsgroup, I noticed a lot of junk messages all over the place. Maybe we could...
20 comments posted 20yrs
posted by comp.arch.fpga.FAQ
20 comments posted 20yrs posted by comp.arch.fpga.FAQ

Timing impossible to meet; PAR stops.

Guys, I'm using ISE 7.1.04i . In PAR I get this error:- ERROR:Par:228 - At least one timing constraint is impossible to...
1 comments posted 20yrs
posted by symon_brewer
1 comments posted 20yrs posted by symon_brewer

Reading user data from PROM

I would like to store user data or configuration data+user data in a PROM that supports a JTAG interface. Do Xilinx PRO...
4 comments posted 20yrs
posted by shubhara0
4 comments posted 20yrs posted by shubhara0

First Impressions of Actel Fusion?

Has anyone got a chance to play with these devices? If so, any first impressions? -Eli
1 comments posted 20yrs
posted by emh203
1 comments posted 20yrs posted by emh203

Actel Fusion

Has anyone got a chance to play with these devices? If so, any first impressions? -Eli
3 comments posted 20yrs
posted by emh203
3 comments posted 20yrs posted by emh203

Virtex II Pro-X Rocket I/O problems

Hi, I'm new to this group - not sure if this question has been answered already... The Xilinx 2Pro-X MGTs suffer from a...
0 comments posted 20yrs
posted by tlnorman
0 comments posted 20yrs posted by tlnorman

Is there someone have the ata controller?

The ata controller in the opencores website don't support the ultra dma mode,but I need the ultra dma mode?Have someone...
1 comments posted 20yrs
posted by bjzhangwn
1 comments posted 20yrs posted by bjzhangwn

VHDL Bus Macro for V2Pro

Dear i am exercising a basic flow of partial configuration from xapp290.pdf In the example (verilog), bm_4b_v2 componen...
0 comments posted 20yrs
posted by pasacco
0 comments posted 20yrs posted by pasacco