Creating Multiple Configuration PROM File

Hello.

Can anyone direct me to a piece of Xilinx literature that explains how to load more than 1 config file into program flash (XCF16P).

Many thanks, Rob

Reply to
Rob
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"Rob" schrieb im Newsbeitrag news:WrhAf.267$ snipped-for-privacy@news01.roc.ny...

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Platform Flash support design revisions but not multi boot

if you need to select which design starts then you need separate controller to select the active revsion this can be small microcontroller or PLD. but then if you have a PLD alredy then it makes more sense to use cheap SPI flash and forget the platfrom flash

xilinx has some PLD based example to control the platform flash, loook at the their web

Antti

Reply to
Antti Lukats

All I want to do is change the select bits on the PROM, initiate a configuration cycle, and have the FPGA loaded with a new/different configuration. Is this possible? If so, how does one create an .mcs file with two configurations? Or is it another file extention?

thank you, rob

Reply to
Rob

"Rob" schrieb im Newsbeitrag news:SFqAf.1387$ snipped-for-privacy@news02.roc.ny...

well that is where you need external microcontroller or PLD to select between active config

you can also select by jumpers but you can not select from FPGA which revision is loaded from Platform Flash

the revision select pins must be controlled by some additional circuitry !!

if you wire them to the FPGA then they are reset to defaults and you can not select which config is loaded

so if you are happy with jumpers selecting the config then its all ok, just add 2 revisions to the PROM when writing it and connect a swithc or jumpers to the rev select pins of the PROM

Antti

Reply to
Antti Lukats

You'll need to use a parallel ROM rather than the serial one so that you can select the configuration. The configuration select needs a little bit of logic outside of the FPGA to hold the configuration select bits while the FPGA is being reconfigured...unless you use partial reconfiguration, in which case you just have to be careful that the part the controls the reconfiguration stays alive. If you go for the partial reconfiguration, you'll still need something outside to bootstrap the initial design that has the configuration controller in it.

I've done whole FPGA configuration with a configuration select on several designs. One of them is documented (although I don't recall there being much detail on the reconfiguration scheme) in my paper on an FPGA based radar environment simulator from about 8 years ago. In that case, a parallel ROM held 16 (I think) FPGA configurations. A CPLD, which IIRC was a Lattice 1032, held the selection registers and the configuration state machine. Configuration in this case was initiated with a command from a VME interface. It managed the configuration of four XC4025E's. The hooks were in the design to allow any of the FPGAs to initiate a reconfiguration, but as I recall we didn't use that capability.

Another one that comes to mind was a universal card reader design on a XC3020 (now I am really dating myself) that would self reconfigure after determining what kind of card was inserted. That one also used a CPLD to manage reconfiguration from a parallel PROM, but in that case it would start up with a default configuration, then when the FPGA application was ready for a reconfiguration, it would output a configuration code and go signal to the CPLD, and the CPLD would then handle the FPGA reconfiguration using a simple state machine.

Those were in the days before Xilinx could do partial reconfiguration, and it worked just fine. So, yes it can be done, and it doesn't take a very complicated external circuit to do it. In fact, I think the PLD and parallel ROM needed actually cost less than the serial ROM for a stock configuration circuit.

Reply to
Ray Andraka

Ray the OP asked for solution using XCF16!

XCF16 can hold 2 designs, but in order to select them the select must be either fixed jumpers or then additional PLD that controls the revision select inputs of the XCF16. Xilinx has a coolrunner design that does that, but in my opinion too, its really nonsense to add a PLD to XCFxxP as the same PLD could also control a SPI flash and provide way more flexibility then the use of XCFxxPP + PLD and would be cheaper as well.

Antti

Reply to
Antti Lukats

Antti,

I missed that he wanted to use an XCF16. I think he would only need 3 bits of a simple PLD to pull it off. My first thought was that the edge of CF and program catches the revision, but it is the rising edge which means by the time that happens the FPGA is alread brain-dead. He just needs to capture the two rev bits in a pair of flip-flops and needs something to toggle program/CF and he should be good to go. If he's got a PLD already on the board for something else, this circuit could go int he corner of the PLD.

Reply to
Ray Andraka

I'm familiar with the hardware setup. What I'm looking for is a document that tells one how to creat the prom file with the tool.

Reply to
Rob

"Rob" schrieb im Newsbeitrag news:4gAAf.357$ snipped-for-privacy@news01.roc.ny...

actually I guessed that, well you just need to start impact and 'enable revisionong' then you can assign different bitstreams to different revisions.

antti

Reply to
Antti Lukats

Antti:

I went through the whole procedure, generated the mult-revision .mcs file, and it doesn't configure the FPGA (V2PRO). I can program the flash (non-revision mode) with either of the 2 config files individulally and configuration works fine.

I have to compress the .bit files of the 2 designs, when generating the multi-revision .mcx file, because two uncompressed .bit files are too big for the XCF16PVO48C PROM that I'm using.

Any thoughts?

Rob

Reply to
Rob

"Rob" schrieb im Newsbeitrag news:BZbBf.525$ snipped-for-privacy@news01.roc.ny...

there are several 'small print' need to know things about the platform flash, check all errata and answer records. you are enabling compress in bitgen options right? there are problems with the compress done by the platform flash, check the platform flash /impact user guide.

sorry I dont know the direct answer. I do know there are issues, also some issues are related to some date codes only so check all relevant materials, if nothing helps open webcase, ie the usual path.well as WebCase support is now done from China I doubt if that brings anything.

For me the platform flash are on DO NOT USE list. I just have worked with them so I know something about them - like details of the programming what is still not published (and will never be) by Xilinx. Had to reverse the algorithm from SVF files :(

Antti

Reply to
Antti Lukats

Antti,

Now that is just not fair.

-snip-

...WebCase support is

That is just not true.

Austin

Reply to
Austin Lesea

Antti, you are smart, energetic, and imaginative, but why do you write such nonsense? You have no reason to assume that TechSupport for US or Europe would come out of China. You just made that up, didn't you ? Hurts your credibility! Peter Alfke

Reply to
Peter Alfke

Antti, you are smart, energetic, and imaginative, but why do you write such nonsense? You have no reason to assume that TechSupport for US or Europe would come out of China. You just made that up, didn't you ? Hurts your credibility! Peter Alfke

Reply to
Peter Alfke

"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@g43g2000cwa.googlegroups.com...

You right Peter,

I am not fair. The life isnt either.

But I am not making anything up. This is something I do not do. (Sure I am wrong sometimes, that has happened).

1) All my latest WebCase's are handled from China or at least from people with chinese names. 2) someone else (I assume from US) reported the same for his 3 last WebCases, he also called and reached answer machine in chinese.

So thats why I assumed that the _global_ WebCase support has been moved to China/chinese. What I said was/is true for me as to my best knowledge of the time of my writing. I did not pay attention to the WebCase email names until someone else pointed my attention to it, then I looked at my cases and I had to agree that its all handled by chinese now. Maybe it isnt, and it was just a co-incident. And sure a superior suport could also be provided from china. Nothing wrong with.

All I was about to say is that I have even less trust (in timely resolved issues) from Xilinx websupport then before (before == when EU support was handled from Ireland and not from China). Maybe China support will be better, only time can tell that, but for the time being I feel that I am my best Xilinx FAE as in vast majority of cases I have had to fix the Xilinx related issues myself.

Like yesterday - I take OPB_SPI core, I set SPI clock ratio, send out 2 bytes to SPI. Works with loopback testing. But with external SPI flash it doesnt work. After hours and hours troubleshooting I connect oscilloscope onto SPI clock and what I see? 7 clocks are normal with programmed clock width then clock pulse of 20 nanoseconds, then again 7 normal clocks and again 20 nanoseconds pulse. Sure this works with loopback test code provided with Xilinx.

For heavens sake there should a way to get something as simple as SPI master to work without the need of connecting an DSO to the FPGA !? I could not belive that 20ns pulse (1 OPB clock). OPB_SPI is part of EDK for long long time, how come this is possible? Has anyone used it before ? Ok, later on I found some xilinx AR as well, talking about clock glitches when data and clock change at the same time. But when I use EDK, and EDK IP cores, I would expect that at least the simplest ones really work, without the need of scoping the signals or searching AR database for related issues. Or is it too much to hope for?

If you work with Xilinx products then things like that happen every other day almost.

I talked about this thing with the fellow engineers around, their comment was: "well thats how they do it, let you to find and fix their problems". Sure this is how MicroSoft does it. This is why so many hate MicroSoft. I like FPGA's. I like very much. But my tolerance level of accepting bugs and erratas is getting lower and lower. I am not getting paid to find bugs. So arent others who open WebCases and help Xilinx to fix their products and services.

I have stated many times that I could be very valuable testing Xilinx software and helping to improve it, I think others here at c.a.f. have made suggestion that I should have early beta test access. I do not. It took me 3 minutes to cause fatal crash close of ISE 8.1 after it was released. If the Xilinx Software goes worse the same rate, I will never install ISE 10.1 on my workstation.

So I am getting more and more frustrated seeing more and more issues with Xilinx products and services. Issues that take my time. Time that I would rather spend with my family or just doing my job, which currently isnt bug hunting.

I am still energetic, and I would love to use all of my smart imagination to improve Xilinx products, but being on the field and just fighting with the Xilinx bugs (while it isnt my job) is not helping Xilinx much. It hurts. Anyone.

I would like to help, but I just dont how.

I have setup open public access bug tracker database where I will enter all the bugs with Xilinx products that I will find. In a small hope that it helps others to save their time to avoid the issues or apply workarounds if those are available.

--
Antti Lukats
http://www.xilant.com
Reply to
Antti Lukats

"Austin Lesea" schrieb im Newsbeitrag news:dr3m9c$ snipped-for-privacy@xco-news.xilinx.com...

Sorry Austin,

sometimes I dont know who is inside of me..

I should have self-censored the post, but I am not making anything up. I commented from my current knowledge. See my longer reply to Peter.

--
Antti Lukats
http://www.xilant.com
Reply to
Antti Lukats

That's quite a large leap, Antti, from 'Chinese name' to 'Must live in China' - did you check the email time tags, that often gives a clue to the time zones you are working between ? China EU is not the most natural choice ?

-jg

Reply to
Jim Granville

maybe I mis-judged. I havent checked the email header time tags. Some else (also having Xilinx issues) was complaining about the answer machine on his WebCase contact to respond in chinese, so I checked the names from emails and found his assumptions about the WebCases now being handled by people with chinese like names to be true.

Maybe I am too hard at (Xilinx WebCase support) as my issues are usually not such that the WebCase assigned person has any chances to help. He always needs to contact others and that makes it really long to get some meaningful response. So I do not really have hopes that a WebCase helps if it is not 'accelerated' but then ah, it makes possible more sense to immediate 'accelerate' the issue, and that is something that Xilinx doesnt like of course. But if immediate acceleration of an issue brings the solution even a few hours faster then it is a few hours won.

I am pretty sure that there are people at Xilinx who are thinking very seriously how to actually improve the software, support and services so lets hope it will get better. There is lots of space for improvements, in all areas.

--
Antti Lukats
http://www.xilant.com
Reply to
Antti Lukats

..and I am sure your web cases send a shudder down any novice support person.. :)

So I do not really have hopes that a WebCase helps if it is not

I think your WEB Bug list is a good idea - Yes, we can understand ISE 8.1i is new SW, and yes there will be issues, but the backward-steps are the real 'eyebrow raisers'.

Seems they suffer the big-company disease, and become too marketing dominated ( and worse, start to believe their own PR spin... )

- so nice public examples of user base problems are things the engineers left within Xilinx can use as leverage to get more resources to do the job properly, are a good thing.

-jg

Reply to
Jim Granville

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