I'm new to this group - not sure if this question has been answered already...
The Xilinx 2Pro-X MGTs suffer from a number of defects. One of them being that the receiver PLL locks up if the incoming serial data disappears, ceases to have the minimum number of transitions, or if it drifts outside a certain frequency range. This is all fine as long as there is a sure-fire recovery mechanism. Xilinx FAEs seem to recommend a reset procedure that affects the transmitted data path as well as the receive - it works for the most part: if the reset procedure is applied while "good" data is injected, it recovers. But the impact to the tx data path is not acceptable in some situations.
Xilinx says to hit the PMA_INIT pin to get the rx to recover.. but this causes a bit of garbage to be output form the transmitter.
Has anyone out there figured out how to get the receiver to lock consistently while not impacting the transmitter? I don't hold out much hope because it seems that Xilinx doesn't know the answer to this question. But if you can help me out here I will be one happy guy.
P.S. Xilinx answer data base #20379 does not help.