Latest threads in Field-Programmable Gate Arrays

VHDL Bus Macro for V2Pro

Dear i am exercising a basic flow of partial configuration from xapp290.pdf In the example (verilog), bm_4b_v2 componen...

0 20yrs

pasacco

0 20yrs pasacco

Security of Xilinx Virtex2 Pro

Hi, I'm considering a VirtexIIPro device for a security sensitive application. This device offers bitstream encryption....

1 20yrs

jetmarc

1 20yrs jetmarc

How in Design Compiler disable writing out "Assign" statement into the netlist?

I was aware that there is a flag which can disenable Design Compiler to write Assign statement. My NCVerilog gave me wa...

2 20yrs

frank.invalid

2 20yrs frank.invalid

Sorting large amounts of floats

Hi, I'm trying to figure out the best way to sort a large amount (thousands) of floats or fixed-point data on an FPGA....

4 20yrs

keith.oconor

4 20yrs keith.oconor

Loading Data from Prom

Hallo, I would store/read datas from a prom. I have connected it to my system using opb_emc. The prom data width is 8 b...

1 20yrs

marc

1 20yrs marc

OT:Shooting Ourselves in the Foot

Here is an observation - what do y'all think ? 1 - Indian / Chinese / East European /etc people are at least as smart a...

328 20yrs

xxx

328 20yrs xxx

Xilinx DDR SDRAM for ML40x

Has anybody ported the Xilinx DDR SDRAM examples over to the ML40x boards?

0 20yrs

bradsmallridge

0 20yrs bradsmallridge

Strange Q1 Output on Xilinx V-4 ISERDES

Dear group, I have a work around for this issue but it seems a little strange that the Q1 from the Master ISERDES is ac...

0 20yrs

bradsmallridge

0 20yrs bradsmallridge

Quadrature Encoder ::

Hi all, Hope everything is fine on your side. Key Words: ML300 board, VHDL, XST, XPS, Xilinx I have written a VHDL prog...

7 20yrs

narashimanc

7 20yrs narashimanc

Bogus Hold Violations with 2X clock on Xilinx ISE 7.1

I have a DCM that drives a 1X clock and 2X clock on BUFGs. In one case, the enable to a CLK2X register depends on a CLK...

0 20yrs

mail

0 20yrs mail

V4 not packing registers into IOBs

Hello Group, I'm having difficulty convincing Xilinx ISE (8.1SP1 WebPack) PAR to pack some of my signals into the IOBs...

4 20yrs

peter

4 20yrs peter

Xilinx padding LC numbers, how do you feel about it?

As we have all known for some time, Xilinx has had a habit of padding the logic cell counts in their data sheets to acc...

77 20yrs

spamgoeshere4

77 20yrs spamgoeshere4

DDR Memory Access Interfact by Virtex-4 FX12

Hi, I just used MIG to generate the memory access interface to the DDR memory. But now I am confused as to how to used...

4 20yrs

agou.win

4 20yrs agou.win

Disabling cross domain checking for Xilinx ISE

Is there an easy to disable timing analysis between two unrelated clocks in ISE 7.1? I don't want to have to put in spe...

2 20yrs

mail

2 20yrs mail

profiling with virtex4 powerpc

Hi, I am working on an ML403 with virtex4 FX12 and ISE7.1i.3 and EDK7.1i.2. I would like to use profiling on the powerp...

0 20yrs

jean-francois.hasson

0 20yrs jean-francois.hasson

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