Has anybody had any showstopping problems when interconnecting Stratix-II and Virtex4 (EP2S180 & LX200) ? We just want to have a mass differential interconnect for a source-synchronous interface on 'left-over' pins for future expansion. Have never used Altera before but I realize the banking is quite different. Also, any experiences good or bad with 10GB Ethernet MAC cores from both Xilinx and Altera ?
Thanks,
-Martin