Greetings, I've used the Altera/Quartus II tool set for a previous project, and my next project will likely use the Xilinx/ISE toolset. In Quartus II there is the ability to define I/O in the top module as virtual pins. This prevented logic from being synthesized away and having the I/O assigned to a real pin on the device. Does anybody now how to do this in the Xilinx/ISE tool set?
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