Hi,
I tried to use MIG to generate the DDR interface for FX12 on ML403 board. And the UCF generated by MIG is not consistent with the one from the ML403 tutorial demo. So I matched it by hand. The address and data bus are OK, but there are
still some pins I don't know. Do you guys know their correspondence? Thanks.
By the way, the DDR ram chip on ML403 is Infineon HYB25D256160BT-7, i.e. 32Mx16bits, 266MHz. And the that on MIG is Micron MT46V32M16P-5B operating at 266MHz, which is also 32Mx16bits. Are they compatible?
# from MIG NET "cntrl0_DDR_CK[0]" LOC = "D2"
; #Bank 6 NET "cntrl0_DDR_CK_N[0]" LOC = "D1" ; #Bank 6 NET "cntrl0_DDR_CK[1]" LOC = "E1"
; #Bank 6 NET "cntrl0_DDR_CK_N[1]" LOC = "F1" ; #Bank 6 NET "cntrl0_READ_EN_IN[0]" LOC = "E9" ; #Bank 6 NET "cntrl0_READ_EN_OUT[0]" LOC = "F9" ; #Bank 6 NET "SYS_CLK_P" LOC = "AF12" ; #Bank 4 NET "SYS_CLK_N" LOC = "AE12" ; #Bank 4 # differential clock used in the idelay_ctrl logic NET "CLK200_P" LOC = "AC10" ; #Bank 4 NET "CLK200_N" LOC = "AB10" ; #Bank 4 #indicate whether the read and write data are the same NET "cntrl0_ERROR" LOC = "W5" ; #Bank 8
#from ML403 tutorial demo NET ddr_ba LOC = B12; # DDR_BA0 NET ddr_ba LOC = A16; # DDR_BA1 NET ddr_casb LOC = F23; # DDR_CAS_N NET ddr_cke LOC = G22; # DDR_CKE NET ddr_csb LOC = G21; # DDR_CS_N NET ddr_rasb LOC = F24; # DDR_RAS_N NET ddr_web LOC = A23; # DDR_WE_N NET ddr_clk LOC = A10; # DDR_CK1_P NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) NET ddr_clkb LOC = B10; # DDR_CK1_N