Field-Programmable Gate Arrays

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FPGA ogg Vorbis/Theora player

i am quite a newbie in FPGA development. my idea is build a SoC(System on Chip) which will be a Video/Audio player base...
3 comments posted 20yrs
posted by uriel.katz
3 comments posted 20yrs posted by uriel.katz

FPGA growth vs. ASIC growth

I have been searching around online for a good comparison of the growth rates of FPGAs and ASICs (specifically gate siz...
19 comments posted 20yrs
posted by dornif
19 comments posted 20yrs posted by dornif

I need your process pictures

Hello everyone I am working on a web site and I need your input to help me build a section of it. This is not a sales p...
1 comments posted 20yrs
posted by dolbowent
1 comments posted 20yrs posted by dolbowent

IP2IP_Addr in IPIF

Hi, group I generated a IPIC interface by the Create and Import Peripheral Wizard to access PLB_DDR blockon the PLB bus...
5 comments posted 20yrs
posted by agou.win
5 comments posted 20yrs posted by agou.win

Source address in IPIC

Hi, group I generated a IPIC interface by the Create and Import Peripheral Wizard to access the memory ports on the PLB...
0 comments posted 20yrs
posted by agou.win
0 comments posted 20yrs posted by agou.win

Microblaze question

Is there any way for a hobbyist to obtain the EDK in order to work w/ Microblaze? Or is there any other way to obtain M...
7 comments posted 20yrs
posted by spammersarevermin
7 comments posted 20yrs posted by spammersarevermin

Modelsim error when doing: port map(a => not(b))

Hi all, I'm VERY sorry because I've seen much discussion about globally static expressions and Modelsim, but I cannot f...
1 comments posted 20yrs
posted by kasty.jose
1 comments posted 20yrs posted by kasty.jose

AC97 Controller

Hi, hope there is anybody who implemented the same: I want to use the AC97 Codec and so i'm trying to implement the Con...
1 comments posted 20yrs
posted by lori
1 comments posted 20yrs posted by lori

high input to CPLD

Hi Friends, I am working on project, where I am using CPLD operating at 5V supply. Can we direcly give the high inut vo...
5 comments posted 20yrs
posted by pradnya.karande
5 comments posted 20yrs posted by pradnya.karande

Mixing and matching related clocks question.

Hi. Quick question for you all. I have a 20MHz FPGA clock and I have some very low frequency periodic actions to take c...
3 comments posted 20yrs
posted by pm940
3 comments posted 20yrs posted by pm940

How will synthesizers handle these statements?

I put these conditions in different always and if-else-if statements, will design compiler & ISE be smart enough to rec...
4 comments posted 20yrs
posted by frank.invalid
4 comments posted 20yrs posted by frank.invalid

BGA central ground matrix

Typically FPGA BGAs have a central square of balls which are all connected to ground. What is the current wisdom on how...
56 comments posted 20yrs
posted by tim
56 comments posted 20yrs posted by tim

Lattice Semiconductor, Lattice Forums Go Live

Dear comp.arch.fpga'rs, Lattice Semiconductor went live with the company's first moderated support forum this week. We...
0 comments posted 20yrs
posted by troy.scott
0 comments posted 20yrs posted by troy.scott

PLB DDR Controller : Sl_rearbitrate issue

Hello, Sometime back there was a question on the comp.arch.fpga about interfacing a PLB master pcore with the PLB DDR c...
1 comments posted 20yrs
posted by njoroge
1 comments posted 20yrs posted by njoroge