I have been searching around online for a good comparison of the growth rates of FPGAs and ASICs (specifically gate size, power consumption per gate, cost per gate, and clock speed). I am trying to show the gap narrowing between these two over time. I have yet to find any good information, and even raw data would be very useful. Is there any such comparison anyone has seen? If not, does anyone know of a good place to find this type of raw data and historical pricing for FPGAs? I seem to be completely unable to find ASIC equivalent gate ratings for most FPGAs.
Why would it narrow? At first sight, it should stay constant. For a given FPGA technology, the differences are simply due to the extra die resources required to implement a programmable feature as opposed to a fixed feature. This difference should stay constant as both the FPGA and ASIC move to new processes.
The obvious differential is that the larger FPGA companies will be able to take advantage of a new process earlier than most ASIC customers. However, as process lifetimes increase (about 5 years now?) this differential decreases, rather than increasing. Besides, it's not in the interest of the fabs to only have a handful of customers on a new process; they want everybody on it.
Another factor to take into account is that the FPGA vendor's cutting-edge devices - the first ones on 90nm, for example - are invariably large, expensive, and low yield, and so probably not useful to most customers. So, it could even be argued that the ability to take advantage of new processes isn't actually that useful anyway.
I suggest to look at the Spartan-3 family, our highest-running 90-nm family. Few designers would call Spartan-3 "large, expensive, and low yield,,,and not useful for most customers" Every new process has a learning curve, but that works in favor of FPGAs, since only they create the enormous volumes that drive yield up and cost down.
In short, FPGA vs ASIC is not a question of technology, but largely of economics and risk tolerance. ASICs are for extreme applications: extreme quantity, extreme complexity, extreme speed, and extremely low power. In most other applications, FPGAs (or other standard parts) are an increasingly popular alternative. I see the FPGA, microprocessor, and ASSP as the obvious choices by default, ASIC is the exception that must be justified in each individual case. But then I admit to being biased... Peter Alfke, Xilinx
Nitpick, but why does the "Application Specific" in "ASIC" apply to an FPGA and not to a Pentium, when the FPGA nails down the specificity of application far less than a processor would?
Well, acronyms are sometimes silly. RAM says random access (which every ROM has), and should really be Read/Write Memory. ASIC seems to stand for a design that is specifically designed for/by one customer, while an ASSP is a standard part for a popular function. Don' read too much into the TLA (three-letter-acronym). Peter Alfke
technically it may not change, but in practice it might for some applications. Unless the ASIC volume is huge I may not make sense to spend the huge NRE to get in the lastest process (what's the price of a 90nm mask set?
500K$?) FPGAs are generic so they have the volume to take advantage of the newest process.
What a deal. Where can you get a 90nm mask set for that price?
We have seen studies that development and productization of a 90nm chip costs from 70 to 180 Million $ (US).
I can not comment on how much it costs Xilinx, but if you look at our R&D spending as a percentage of revenues from our public stock and business reports, those numbers are in the right magnitude range.
Like they say about Opera, it is all over when the fat lady sings. So it is with ASICs "heyday". The singing is over. The growth is entirely negative. The ASIC starts are shrinking by a factor of ten per year.
Now ASSPs are still doing very well, as a standard product still is a money maker, even with these high development costs. And a standard product costs a lot less when the die is 1/2 the area in the latest technology....
To be fair, almost nobody spends these figures. You can get into the ASIC game for as little as $100K in NRE plus, say, $50K in tools. All those graphs I've ever seen showing a cross-over point at 10's of K pieces are complete nonsense. These are real numbers for a .11um structured ASIC.
Well, no, and nor would I; I like them. If you want to know what I mean try to get sensible quotes and lead times on an XC4VFX20, XC4VFX40 or XC4VLX80 (not random choices - three I've tried to get quotes on recently).
Not exactly fair. I've spent a lot of time looking (and doing), and my rule of thumbs are, more or less:
1) FPGAs top out at about 750K 'real' gates, and about 40-80MHz real system speeds. Anything beyond this is too expensive (unless you've got *really* small volumes) or too difficult. Yes, I know everybody is going to argue about the exact figures.
2) 1M - ~4M 'real' gates, 75-250MHz, ~1500 pcs/yr for 3 years =>
structured ASIC, no brainer
3) 4M+ gates, 300MHz+, ~3K pcs/yr for 3 years => standard cell
4) If you're going to spend $500K over 3 years (NRE + device costs) then the structured ASIC vendors will talk to you
5) If you're going to spend $1M over 3 years (NRE + device costs) then the standard cell vendors will talk to you
Of course, for options 2- 5 you need to buy real tools, and you need to know how to verify.
Indeed... :)
PS - if anybody out there wants to subcontract a structured ASIC conversion, reply and I'll send you a real email address. Sorry, Peter... :)
The big dedicated players, LSI Logic, Xilinx, Altera, Lattice, Actel, et.al. are all publicly traded companies. If you want to check on their success, just watch their relative stock performance. The beauty of capitalism: hot air does not help, the Bottom Line speaks clearly. Peter Alfke
Have you actually got a quote for a 90nm mask set? Can you find a real number on the web for a real mask price? I'm willing to bet the answer to both of those is no. $500K was the standard figure going around the web 5 years ago, when 90nm was new. And how many masks did that cover?
35? How many masks does the average ASIC developer pay for? 5?
According to Gartner Dataquest, 20% of all design starts in the Americas are now at 90nm. Correct me if I'm wrong, but my guess is that Xilinx is responsible for about 1% of design starts in the Americas. The other guys are not paying 70 - $180M.
Austin, that's just nonsense. No-one has the real numbers, but there is general agreement - IIRC, it's about a year since I collected the figures - that starts have dropped from ~10k/year to a figure of between 2K and 4K/year, *over 5 years*. The analyst who came came up with the 2K figure also ignored ASSPs, which makes no sense. ASSPs
*are* ASICs. He's also ignored the fact that ASIC starts are clearly going to decrease because people roll a number of existing devices into one larger device. The figures were also compiled at a time when no-one was going into 90nm because of the complexity. See any number of commentaries by Gartner. Everyone knows that the real revenue is in ASICs, not FPGAs. Gartner also says that the ASIC market *grew* 11% in
2004.
FPGAs form a small part of the totality of ASSPs. IIRC, there are currently about 2000 ASSP design starts a year. And yes, of course, they all get better in new technologies.
Come on, guys, this is not a Xilinx marketing forum. Perhaps you could credit us with a little more intelligence.
Credit me with knowing what I know, and I'll credit you with what you know.
ASIC starts are decreasing. Fact.
FPGA "starts" are increasing. Also a fact.
By how much, and when, is variable depending on who you quote.
My opinion is it is going down the tubes pretty fast. Your opinion is that it is not (if you include ASSP's).
I don't include ASSP's, as they are not our primary competition. We are making inroads into embedded computing, and extreme DSP, as well as taking more sockets that would have been ASICs (if the customer could afford it).
I have had customers come to visit. They say "we can't afford to make ASICs any longer, we need to learn how to use your FPGAs." These are not little companies. These a multinational corporations with sites around the world.
My job is tougher because now I have to explain to folks who used to design ASICs for a living. They KNOW all of the terrible ultra deep submicron potholes. And they (sometimes) do not give us any credit for having also experienced all the potholes, and already gotten around them. They somehow feel that making FPGas is easy. Well, many have tried, and most have failed. Must be trivial, right?
Paul, don't get offended. You were the one who stoked the fire. The OP asked for a technical comparison between FPGAs and ASICs. And I interpret that as a comparison between customer-specific designs (Leaving out microprocessors, and ASSP, since they serve a different market requirement. If uPs and/or ASSPs fill the need, anybody would be a fool for not using them.) So the comparison here is only between two different ways to achieve a custom hardware solution: FPGAs or ASICs. The relative merits have been described ad nauseam. My point was that you cannot discuss this without mentioning economics. And economics more and more favor FPGAs, as Moore's Law drives all of us to smaller geometries. This may sound like Xilinx Marketing, but it also happens to be a fact. The ASIC market is still big, but relative to FPGAs it is shrinking, especially when you look at the number of new design starts. There will alays be a market for both methods, but the old religion of "Real men do ASICs" is fading, similar to Jerry Sanders' "Real men have fabs". We have all got smarter with time. Peter Alfke
Not so much on rates of change, but for a 90nm point comparison, see the paper by Kuon and Rose about to be published in FPGA next month. There the comparison is standard-cell ASIC to Stratix-II or similar.
I agree (apart from the assertion that I 'stoked the fire'!). The OP appeared, from what I could see, to be asking how the relative technical merit scaled with generations. I replied that it was my opinion that the relative technical difference probably stays constant over generations. You introduced the economics, and I made the point that there were 2 sides to the economics story, and I gave some real figures to back that up.
But yes, I was irritated by Austin's claim that ASIC starts are decreasing by a factor of 10 a year. It's not even possible given that there were only 10K starts a year maybe 7 years ago. It's also of debatable relevance, given that a start at 90 or 110nm is going to contain a lot more logic than a start at 130 or 180.
Yes, a comparison of technical merit between generations is what I was looking for. I am trying to support (or help reject) the conjecture that as time goes on, FPGAs are becoming a more viable alternative to traditional ASICs. With this in mind, I'm trying to cover all aspects of what would make them a viable alternative or not--which seem to be size per gate, cost per gate (not including NRE), power usage per gate, and clock speed. I am trying to avoid market speculation.
Comparing FPGAs and ASICs seems to be a hard comparison to make (even when just comparing current generation technology), especially as measurements such as "total gates" become more abstract. The best way to do this comparison seems to be benchmarking various designs implemented on ASICs and FPGAs. Creating such benchmarks myself is way beyond the scope of what I am doing, so I am left looking for someone else's report or data.
Also, Kuon and Rose's paper seems to cover many of the things I was looking for.
I appreciate all the input so far from everyone, and I am sorry for the late reply (I have been away most of the weekend).
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