Hi. Quick question for you all.
I have a 20MHz FPGA clock and I have some very low frequency periodic actions to take care of so I want to generate an approximate 10Hz clock to give to the modules that need it so they don't need their own big wide counters.
module slowclk(input clk, output slowclk); reg [19:0] cnt = 29'h0;
assign slowclk = cnt[19];
always @(posedge clk) cnt
It's safer and easier to analyze if you keep thing in one clock domain. Change your code to be:
module slowclk(input clk, output slow_pulse); reg [19:0] cnt = 29'h0;
assign slow_pulse = cnt[19];
always @(posedge clk) if (slow_pulse) cnt
The clocks are _almost_ in phase. slowclk will be delayed from clk due to the clock to Q of counter bit cnt[19] and the global buffer that gets thrown in unless you specify otherwise.
At 20 MHz, you generally won't have setup time ussues with passing x to the fast process. You may still want to put in a FROM : TO style timing constraint to make sure of this.
The usual problem here is hold time violations going from the fast process to the slow one. If your (expression) in the slow process uses any outputs of the fast process, then you can have hold time violations due to the slowclk delay. Note that the skew times in your timing report are within each clock domain and don't indicate skew between the two clocks.
Good luck, Gabor
I see. Thanks the for explanation Gabor. Perhaps I'm better off using John's idea.
Regards, Paul.
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