Hello all,
I have a problem with internal tristates in Xilinx Virtex-2. They basically don't exist, although are widely used in the documentation. Imagine you have N dual port rams with the enable inputs attached to the output of a tristate like this:
g_loop: for x in 0 to N-1 generate nEnable(x)
One option is to permanently drive the tri-state bus with "H".
- Brian
Thanks Brian, that works. Just one hint: the line driving the bus to 'H' must be enclosed between "synopsys translate_off" and "synopsys translate_on" metacommands. Like this:
g_loop: for x in 0 to N-1 generate nEnable(x)
A very good idea. (Of course I thought about it just after posting)
To some extent, this is a tools issue. I seem to recall Leonardo coping with this, as it should, but your suggestion is good practice anyway.
- Brian
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