I generated a IPIC interface by the Create and Import Peripheral Wizard to access the memory ports on the PLB bus.
I chose the DMA, user logic Master Support mode. And then try to develop my own logic based on the generated files. Here, I have one problem:
To write to an address on PLB bus, I need to provide two addresses: local address which stores the source data and the destination address to which writes the data. So I think I need to instantiate a BRAM in the FPGA to provide the source address. What I am not clear is whether the BRAM is compatible the IPIC logic. Here I only local address signal to be connected to BRAM, and how to do with the left input/output ports on the BRAM.
Are there any other ways to offer an address which could serve as the source for the IPIC?
Thank you for the help. Roger